119 static void reg_w1(struct gspca_dev *gspca_dev,  in reg_w1()  function
149 	reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Open);  in tv_8532WriteEEprom()
151 		reg_w1(gspca_dev, R03_TABLE_ADDR, i);  in tv_8532WriteEEprom()
152 		reg_w1(gspca_dev, R04_WTRAM_DATA_L, eeprom_data[i][2]);  in tv_8532WriteEEprom()
153 		reg_w1(gspca_dev, R05_WTRAM_DATA_M, eeprom_data[i][1]);  in tv_8532WriteEEprom()
154 		reg_w1(gspca_dev, R06_WTRAM_DATA_H, eeprom_data[i][0]);  in tv_8532WriteEEprom()
155 		reg_w1(gspca_dev, R08_RAM_WRITE_ACTION, 0);  in tv_8532WriteEEprom()
157 	reg_w1(gspca_dev, R07_TABLE_LEN, i);  in tv_8532WriteEEprom()
158 	reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Close);  in tv_8532WriteEEprom()
176 	reg_w1(gspca_dev, R3B_Test3, 0x0a);	/* Test0Sel = 10 */  in tv_8532_setReg()
178 	reg_w1(gspca_dev, R0E_AD_HEIGHTL, 0x90);  in tv_8532_setReg()
179 	reg_w1(gspca_dev, R0F_AD_HEIGHTH, 0x01);  in tv_8532_setReg()
181 	reg_w1(gspca_dev, R10_AD_COL_BEGINL, 0x44);  in tv_8532_setReg()
183 	reg_w1(gspca_dev, R11_AD_COL_BEGINH, 0x00);  in tv_8532_setReg()
185 	reg_w1(gspca_dev, R14_AD_ROW_BEGINL, 0x0a);  in tv_8532_setReg()
187 	reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x02);  in tv_8532_setReg()
188 	reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x00);  in tv_8532_setReg()
189 	reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);  in tv_8532_setReg()
204 	reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);  in setexposure()
221 	reg_w1(gspca_dev, R0C_AD_WIDTHL, 0xe8);		/* 0x20; 0x0c */  in sd_start()
222 	reg_w1(gspca_dev, R0D_AD_WIDTHH, 0x03);  in sd_start()
225 	reg_w1(gspca_dev, R28_QUANT, 0x90);  in sd_start()
229 		reg_w1(gspca_dev, R29_LINE, 0x41);  in sd_start()
233 		reg_w1(gspca_dev, R29_LINE, 0x81);  in sd_start()
237 	reg_w1(gspca_dev, R2C_POLARITY, 0x10);		/* slow clock */  in sd_start()
238 	reg_w1(gspca_dev, R2D_POINT, 0x14);  in sd_start()
239 	reg_w1(gspca_dev, R2E_POINTH, 0x01);  in sd_start()
240 	reg_w1(gspca_dev, R2F_POINTB, 0x12);  in sd_start()
241 	reg_w1(gspca_dev, R30_POINTBH, 0x01);  in sd_start()
246 	reg_w1(gspca_dev, R31_UPD, 0x01);	/* update registers */  in sd_start()
248 	reg_w1(gspca_dev, R31_UPD, 0x00);	/* end update */  in sd_start()
258 	reg_w1(gspca_dev, R3B_Test3, 0x0b);	/* Test0Sel = 11 = GPIO */  in sd_stopN()