57 	int ret;  in mxl1x1sf_soft_reset()  local
60 	ret = mxl111sf_write_reg(state, 0xff, 0x00); /* AIC */  in mxl1x1sf_soft_reset()
61 	if (mxl_fail(ret))  in mxl1x1sf_soft_reset()
63 	ret = mxl111sf_write_reg(state, 0x02, 0x01); /* get out of reset */  in mxl1x1sf_soft_reset()
64 	mxl_fail(ret);  in mxl1x1sf_soft_reset()
66 	return ret;  in mxl1x1sf_soft_reset()
71 	int ret;  in mxl1x1sf_set_device_mode()  local
77 	ret = mxl111sf_write_reg(state, 0x03,  in mxl1x1sf_set_device_mode()
79 	if (mxl_fail(ret))  in mxl1x1sf_set_device_mode()
82 	ret = mxl111sf_write_reg_mask(state,  in mxl1x1sf_set_device_mode()
88 	if (mxl_fail(ret))  in mxl1x1sf_set_device_mode()
93 	return ret;  in mxl1x1sf_set_device_mode()
126 	int ret;  in mxl111sf_config_mpeg_in()  local
133 	ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX);  in mxl111sf_config_mpeg_in()
134 	mxl_fail(ret);  in mxl111sf_config_mpeg_in()
144 	ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode);  in mxl111sf_config_mpeg_in()
145 	mxl_fail(ret);  in mxl111sf_config_mpeg_in()
149 	ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode);  in mxl111sf_config_mpeg_in()
150 	mxl_fail(ret);  in mxl111sf_config_mpeg_in()
168 		ret = mxl111sf_read_reg(state,  in mxl111sf_config_mpeg_in()
171 		mxl_fail(ret);  in mxl111sf_config_mpeg_in()
178 		ret = mxl111sf_write_reg(state,  in mxl111sf_config_mpeg_in()
181 		mxl_fail(ret);  in mxl111sf_config_mpeg_in()
196 	ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode);  in mxl111sf_config_mpeg_in()
197 	mxl_fail(ret);  in mxl111sf_config_mpeg_in()
199 	return ret;  in mxl111sf_config_mpeg_in()
218 	int ret;  in mxl111sf_init_i2s_port()  local
222 	ret = mxl111sf_ctrl_program_regs(state, init_i2s);  in mxl111sf_init_i2s_port()
223 	if (mxl_fail(ret))  in mxl111sf_init_i2s_port()
226 	ret = mxl111sf_write_reg(state, V6_I2S_NUM_SAMPLES_REG, sample_size);  in mxl111sf_init_i2s_port()
227 	mxl_fail(ret);  in mxl111sf_init_i2s_port()
229 	return ret;  in mxl111sf_init_i2s_port()
247 	int ret;  in mxl111sf_config_i2s()  local
252 	ret = mxl111sf_read_reg(state, V6_I2S_STREAM_START_BIT_REG, &tmp);  in mxl111sf_config_i2s()
253 	if (mxl_fail(ret))  in mxl111sf_config_i2s()
258 	ret = mxl111sf_write_reg(state, V6_I2S_STREAM_START_BIT_REG, tmp);  in mxl111sf_config_i2s()
259 	if (mxl_fail(ret))  in mxl111sf_config_i2s()
262 	ret = mxl111sf_read_reg(state, V6_I2S_STREAM_END_BIT_REG, &tmp);  in mxl111sf_config_i2s()
263 	if (mxl_fail(ret))  in mxl111sf_config_i2s()
268 	ret = mxl111sf_write_reg(state, V6_I2S_STREAM_END_BIT_REG, tmp);  in mxl111sf_config_i2s()
269 	mxl_fail(ret);  in mxl111sf_config_i2s()
271 	return ret;  in mxl111sf_config_i2s()
277 	int ret;  in mxl111sf_config_spi()  local
281 	ret = mxl111sf_write_reg(state, 0x00, 0x02);  in mxl111sf_config_spi()
282 	if (mxl_fail(ret))  in mxl111sf_config_spi()
285 	ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val);  in mxl111sf_config_spi()
286 	if (mxl_fail(ret))  in mxl111sf_config_spi()
294 	ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val);  in mxl111sf_config_spi()
295 	if (mxl_fail(ret))  in mxl111sf_config_spi()
298 	ret = mxl111sf_write_reg(state, 0x00, 0x00);  in mxl111sf_config_spi()
299 	mxl_fail(ret);  in mxl111sf_config_spi()
301 	return ret;  in mxl111sf_config_spi()
308 	int ret;  in mxl111sf_idac_config()  local
328 		ret = mxl111sf_write_reg(state, V6_IDAC_HYSTERESIS_REG,  in mxl111sf_idac_config()
330 		mxl_fail(ret);  in mxl111sf_idac_config()
333 	ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val);  in mxl111sf_idac_config()
334 	mxl_fail(ret);  in mxl111sf_idac_config()
336 	return ret;  in mxl111sf_idac_config()