Lines Matching refs:ret
66 int ret; in reg_write() local
68 ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf)); in reg_write()
69 if (ret >= 0 && ret < sizeof(wbuf)) in reg_write()
70 ret = -EIO; in reg_write()
71 return (ret == sizeof(wbuf)) ? 0 : ret; in reg_write()
90 int ret; in reg_read() local
92 ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs)); in reg_read()
93 if (ret >= 0 && ret < ARRAY_SIZE(msgs)) in reg_read()
94 ret = -EIO; in reg_read()
95 return (ret == ARRAY_SIZE(msgs)) ? 0 : ret; in reg_read()
111 int ret; in qm1d1c0042_wakeup() local
116 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_wakeup()
117 if (ret == 0) in qm1d1c0042_wakeup()
118 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_wakeup()
120 if (ret < 0) in qm1d1c0042_wakeup()
123 return ret; in qm1d1c0042_wakeup()
182 int i, ret; in qm1d1c0042_set_params() local
204 ret = reg_write(state, 0x02, val); in qm1d1c0042_set_params()
205 if (ret < 0) in qm1d1c0042_set_params()
206 return ret; in qm1d1c0042_set_params()
212 ret = reg_write(state, 0x06, state->regs[0x06]); in qm1d1c0042_set_params()
213 if (ret < 0) in qm1d1c0042_set_params()
214 return ret; in qm1d1c0042_set_params()
218 ret = reg_write(state, 0x07, state->regs[0x07]); in qm1d1c0042_set_params()
219 if (ret < 0) in qm1d1c0042_set_params()
220 return ret; in qm1d1c0042_set_params()
229 ret = reg_write(state, 0x08, val); in qm1d1c0042_set_params()
230 if (ret < 0) in qm1d1c0042_set_params()
231 return ret; in qm1d1c0042_set_params()
250 ret = reg_write(state, 0x09, state->regs[0x09]); in qm1d1c0042_set_params()
251 if (ret == 0) in qm1d1c0042_set_params()
252 ret = reg_write(state, 0x0a, state->regs[0x0a]); in qm1d1c0042_set_params()
253 if (ret == 0) in qm1d1c0042_set_params()
254 ret = reg_write(state, 0x0b, state->regs[0x0b]); in qm1d1c0042_set_params()
255 if (ret != 0) in qm1d1c0042_set_params()
256 return ret; in qm1d1c0042_set_params()
260 ret = reg_write(state, 0x13, state->regs[0x13]); in qm1d1c0042_set_params()
261 if (ret < 0) in qm1d1c0042_set_params()
262 return ret; in qm1d1c0042_set_params()
268 ret = reg_write(state, 0x0c, val); in qm1d1c0042_set_params()
269 if (ret < 0) in qm1d1c0042_set_params()
270 return ret; in qm1d1c0042_set_params()
273 ret = reg_write(state, 0x0c, val); in qm1d1c0042_set_params()
274 if (ret < 0) in qm1d1c0042_set_params()
275 return ret; in qm1d1c0042_set_params()
286 ret = reg_write(state, 0x08, 0x09); in qm1d1c0042_set_params()
287 if (ret < 0) in qm1d1c0042_set_params()
288 return ret; in qm1d1c0042_set_params()
291 ret = reg_write(state, 0x13, state->regs[0x13]); in qm1d1c0042_set_params()
292 if (ret < 0) in qm1d1c0042_set_params()
293 return ret; in qm1d1c0042_set_params()
301 int ret; in qm1d1c0042_sleep() local
307 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_sleep()
308 if (ret == 0) in qm1d1c0042_sleep()
309 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_sleep()
310 if (ret < 0) in qm1d1c0042_sleep()
313 return ret; in qm1d1c0042_sleep()
320 int i, ret; in qm1d1c0042_init() local
328 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */ in qm1d1c0042_init()
329 if (ret < 0) in qm1d1c0042_init()
334 ret = reg_write(state, 0x01, val); /* soft reset off */ in qm1d1c0042_init()
335 if (ret < 0) in qm1d1c0042_init()
339 ret = reg_read(state, 0x00, &val); in qm1d1c0042_init()
340 if (ret < 0 || val != 0x48) in qm1d1c0042_init()
345 ret = reg_write(state, 0x0c, state->regs[0x0c]); in qm1d1c0042_init()
346 if (ret < 0) in qm1d1c0042_init()
352 ret = reg_write(state, i, state->regs[i]); in qm1d1c0042_init()
353 if (ret < 0) in qm1d1c0042_init()
357 ret = reg_write(state, i, state->regs[i]); in qm1d1c0042_init()
358 if (ret < 0) in qm1d1c0042_init()
362 ret = qm1d1c0042_wakeup(state); in qm1d1c0042_init()
363 if (ret < 0) in qm1d1c0042_init()
366 ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch); in qm1d1c0042_init()
367 if (ret < 0) in qm1d1c0042_init()
370 return ret; in qm1d1c0042_init()
375 return ret; in qm1d1c0042_init()