89 static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)  in hix5hd2_ir_config()  argument
94 	writel_relaxed(0x01, priv->base + IR_ENABLE);  in hix5hd2_ir_config()
95 	while (readl_relaxed(priv->base + IR_BUSY)) {  in hix5hd2_ir_config()
99 			dev_err(priv->dev, "IR_BUSY timeout\n");  in hix5hd2_ir_config()
105 	rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);  in hix5hd2_ir_config()
112 	writel_relaxed(val, priv->base + IR_CONFIG);  in hix5hd2_ir_config()
114 	writel_relaxed(0x00, priv->base + IR_INTM);  in hix5hd2_ir_config()
116 	writel_relaxed(0x01, priv->base + IR_START);  in hix5hd2_ir_config()
122 	struct hix5hd2_ir_priv *priv = rdev->priv;  in hix5hd2_ir_open()  local
124 	hix5hd2_ir_enable(priv, true);  in hix5hd2_ir_open()
125 	return hix5hd2_ir_config(priv);  in hix5hd2_ir_open()
130 	struct hix5hd2_ir_priv *priv = rdev->priv;  in hix5hd2_ir_close()  local
132 	hix5hd2_ir_enable(priv, false);  in hix5hd2_ir_close()
140 	struct hix5hd2_ir_priv *priv = data;  in hix5hd2_ir_rx_interrupt()  local
142 	irq_sr = readl_relaxed(priv->base + IR_INTS);  in hix5hd2_ir_rx_interrupt()
149 		ir_raw_event_reset(priv->rdev);  in hix5hd2_ir_rx_interrupt()
150 		symb_num = readl_relaxed(priv->base + IR_DATAH);  in hix5hd2_ir_rx_interrupt()
152 			readl_relaxed(priv->base + IR_DATAL);  in hix5hd2_ir_rx_interrupt()
154 		writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);  in hix5hd2_ir_rx_interrupt()
155 		dev_info(priv->dev, "overflow, level=%d\n",  in hix5hd2_ir_rx_interrupt()
162 		symb_num = readl_relaxed(priv->base + IR_DATAH);  in hix5hd2_ir_rx_interrupt()
164 			symb_val = readl_relaxed(priv->base + IR_DATAL);  in hix5hd2_ir_rx_interrupt()
171 			ir_raw_event_store(priv->rdev, &ev);  in hix5hd2_ir_rx_interrupt()
176 				ir_raw_event_store(priv->rdev, &ev);  in hix5hd2_ir_rx_interrupt()
178 				ir_raw_event_set_idle(priv->rdev, true);  in hix5hd2_ir_rx_interrupt()
183 			writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);  in hix5hd2_ir_rx_interrupt()
185 			writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);  in hix5hd2_ir_rx_interrupt()
189 	ir_raw_event_handle(priv->rdev);  in hix5hd2_ir_rx_interrupt()
198 	struct hix5hd2_ir_priv *priv;  in hix5hd2_ir_probe()  local
203 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);  in hix5hd2_ir_probe()
204 	if (!priv)  in hix5hd2_ir_probe()
207 	priv->regmap = syscon_regmap_lookup_by_phandle(node,  in hix5hd2_ir_probe()
209 	if (IS_ERR(priv->regmap)) {  in hix5hd2_ir_probe()
215 	priv->base = devm_ioremap_resource(dev, res);  in hix5hd2_ir_probe()
216 	if (IS_ERR(priv->base))  in hix5hd2_ir_probe()
217 		return PTR_ERR(priv->base);  in hix5hd2_ir_probe()
219 	priv->irq = platform_get_irq(pdev, 0);  in hix5hd2_ir_probe()
220 	if (priv->irq < 0) {  in hix5hd2_ir_probe()
222 		return priv->irq;  in hix5hd2_ir_probe()
229 	priv->clock = devm_clk_get(dev, NULL);  in hix5hd2_ir_probe()
230 	if (IS_ERR(priv->clock)) {  in hix5hd2_ir_probe()
232 		ret = PTR_ERR(priv->clock);  in hix5hd2_ir_probe()
235 	clk_prepare_enable(priv->clock);  in hix5hd2_ir_probe()
236 	priv->rate = clk_get_rate(priv->clock);  in hix5hd2_ir_probe()
240 	rdev->priv = priv;  in hix5hd2_ir_probe()
259 	if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt,  in hix5hd2_ir_probe()
260 			     0, pdev->name, priv) < 0) {  in hix5hd2_ir_probe()
261 		dev_err(dev, "IRQ %d register failed\n", priv->irq);  in hix5hd2_ir_probe()
266 	priv->rdev = rdev;  in hix5hd2_ir_probe()
267 	priv->dev = dev;  in hix5hd2_ir_probe()
268 	platform_set_drvdata(pdev, priv);  in hix5hd2_ir_probe()
276 	clk_disable_unprepare(priv->clock);  in hix5hd2_ir_probe()
285 	struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev);  in hix5hd2_ir_remove()  local
287 	clk_disable_unprepare(priv->clock);  in hix5hd2_ir_remove()
288 	rc_unregister_device(priv->rdev);  in hix5hd2_ir_remove()
295 	struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);  in hix5hd2_ir_suspend()  local
297 	clk_disable_unprepare(priv->clock);  in hix5hd2_ir_suspend()
298 	hix5hd2_ir_enable(priv, false);  in hix5hd2_ir_suspend()
305 	struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);  in hix5hd2_ir_resume()  local
307 	hix5hd2_ir_enable(priv, true);  in hix5hd2_ir_resume()
308 	clk_prepare_enable(priv->clock);  in hix5hd2_ir_resume()
310 	writel_relaxed(0x01, priv->base + IR_ENABLE);  in hix5hd2_ir_resume()
311 	writel_relaxed(0x00, priv->base + IR_INTM);  in hix5hd2_ir_resume()
312 	writel_relaxed(0xff, priv->base + IR_INTC);  in hix5hd2_ir_resume()
313 	writel_relaxed(0x01, priv->base + IR_START);  in hix5hd2_ir_resume()