22 static inline u32 vp_read(struct mxr_device *mdev, u32 reg_id)  in vp_read()  argument
24 	return readl(mdev->res.vp_regs + reg_id);  in vp_read()
27 static inline void vp_write(struct mxr_device *mdev, u32 reg_id, u32 val)  in vp_write()  argument
29 	writel(val, mdev->res.vp_regs + reg_id);  in vp_write()
32 static inline void vp_write_mask(struct mxr_device *mdev, u32 reg_id,  in vp_write_mask()  argument
35 	u32 old = vp_read(mdev, reg_id);  in vp_write_mask()
38 	writel(val, mdev->res.vp_regs + reg_id);  in vp_write_mask()
41 static inline u32 mxr_read(struct mxr_device *mdev, u32 reg_id)  in mxr_read()  argument
43 	return readl(mdev->res.mxr_regs + reg_id);  in mxr_read()
46 static inline void mxr_write(struct mxr_device *mdev, u32 reg_id, u32 val)  in mxr_write()  argument
48 	writel(val, mdev->res.mxr_regs + reg_id);  in mxr_write()
51 static inline void mxr_write_mask(struct mxr_device *mdev, u32 reg_id,  in mxr_write_mask()  argument
54 	u32 old = mxr_read(mdev, reg_id);  in mxr_write_mask()
57 	writel(val, mdev->res.mxr_regs + reg_id);  in mxr_write_mask()
60 void mxr_vsync_set_update(struct mxr_device *mdev, int en)  in mxr_vsync_set_update()  argument
63 	mxr_write_mask(mdev, MXR_STATUS, en ? MXR_STATUS_SYNC_ENABLE : 0,  in mxr_vsync_set_update()
65 	vp_write(mdev, VP_SHADOW_UPDATE, en ? VP_SHADOW_UPDATE_ENABLE : 0);  in mxr_vsync_set_update()
68 static void __mxr_reg_vp_reset(struct mxr_device *mdev)  in __mxr_reg_vp_reset()  argument
72 	vp_write(mdev, VP_SRESET, VP_SRESET_PROCESSING);  in __mxr_reg_vp_reset()
75 		if (~vp_read(mdev, VP_SRESET) & VP_SRESET_PROCESSING)  in __mxr_reg_vp_reset()
82 static void mxr_reg_vp_default_filter(struct mxr_device *mdev);
84 void mxr_reg_reset(struct mxr_device *mdev)  in mxr_reg_reset()  argument
89 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_reset()
90 	mxr_vsync_set_update(mdev, MXR_DISABLE);  in mxr_reg_reset()
93 	mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);  in mxr_reg_reset()
96 	mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,  in mxr_reg_reset()
108 	mxr_write(mdev, MXR_LAYER_CFG, val);  in mxr_reg_reset()
111 	mxr_write(mdev, MXR_BG_COLOR0, 0x808080);  in mxr_reg_reset()
112 	mxr_write(mdev, MXR_BG_COLOR1, 0x808080);  in mxr_reg_reset()
113 	mxr_write(mdev, MXR_BG_COLOR2, 0x808080);  in mxr_reg_reset()
122 	mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);  in mxr_reg_reset()
123 	mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);  in mxr_reg_reset()
126 	__mxr_reg_vp_reset(mdev);  in mxr_reg_reset()
127 	mxr_reg_vp_default_filter(mdev);  in mxr_reg_reset()
130 	mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);  in mxr_reg_reset()
132 	mxr_vsync_set_update(mdev, MXR_ENABLE);  in mxr_reg_reset()
133 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_reset()
136 void mxr_reg_graph_format(struct mxr_device *mdev, int idx,  in mxr_reg_graph_format()  argument
142 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_graph_format()
143 	mxr_vsync_set_update(mdev, MXR_DISABLE);  in mxr_reg_graph_format()
146 	mxr_write_mask(mdev, MXR_GRAPHIC_CFG(idx),  in mxr_reg_graph_format()
150 	mxr_write(mdev, MXR_GRAPHIC_SPAN(idx), geo->src.full_width);  in mxr_reg_graph_format()
155 	mxr_write(mdev, MXR_GRAPHIC_WH(idx), val);  in mxr_reg_graph_format()
160 	mxr_write(mdev, MXR_GRAPHIC_SXY(idx), val);  in mxr_reg_graph_format()
165 	mxr_write(mdev, MXR_GRAPHIC_DXY(idx), val);  in mxr_reg_graph_format()
167 	mxr_vsync_set_update(mdev, MXR_ENABLE);  in mxr_reg_graph_format()
168 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_graph_format()
171 void mxr_reg_vp_format(struct mxr_device *mdev,  in mxr_reg_vp_format()  argument
176 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_vp_format()
177 	mxr_vsync_set_update(mdev, MXR_DISABLE);  in mxr_reg_vp_format()
179 	vp_write_mask(mdev, VP_MODE, fmt->cookie, VP_MODE_FMT_MASK);  in mxr_reg_vp_format()
182 	vp_write(mdev, VP_IMG_SIZE_Y, VP_IMG_HSIZE(geo->src.full_width) |  in mxr_reg_vp_format()
185 	vp_write(mdev, VP_IMG_SIZE_C, VP_IMG_HSIZE(geo->src.full_width) |  in mxr_reg_vp_format()
188 	vp_write(mdev, VP_SRC_WIDTH, geo->src.width);  in mxr_reg_vp_format()
189 	vp_write(mdev, VP_SRC_HEIGHT, geo->src.height);  in mxr_reg_vp_format()
190 	vp_write(mdev, VP_SRC_H_POSITION,  in mxr_reg_vp_format()
192 	vp_write(mdev, VP_SRC_V_POSITION, geo->src.y_offset);  in mxr_reg_vp_format()
194 	vp_write(mdev, VP_DST_WIDTH, geo->dst.width);  in mxr_reg_vp_format()
195 	vp_write(mdev, VP_DST_H_POSITION, geo->dst.x_offset);  in mxr_reg_vp_format()
197 		vp_write(mdev, VP_DST_HEIGHT, geo->dst.height / 2);  in mxr_reg_vp_format()
198 		vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset / 2);  in mxr_reg_vp_format()
200 		vp_write(mdev, VP_DST_HEIGHT, geo->dst.height);  in mxr_reg_vp_format()
201 		vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset);  in mxr_reg_vp_format()
204 	vp_write(mdev, VP_H_RATIO, geo->x_ratio);  in mxr_reg_vp_format()
205 	vp_write(mdev, VP_V_RATIO, geo->y_ratio);  in mxr_reg_vp_format()
207 	vp_write(mdev, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);  in mxr_reg_vp_format()
209 	mxr_vsync_set_update(mdev, MXR_ENABLE);  in mxr_reg_vp_format()
210 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_vp_format()
214 void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr)  in mxr_reg_graph_buffer()  argument
219 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_graph_buffer()
220 	mxr_vsync_set_update(mdev, MXR_DISABLE);  in mxr_reg_graph_buffer()
223 		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);  in mxr_reg_graph_buffer()
225 		mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);  in mxr_reg_graph_buffer()
226 	mxr_write(mdev, MXR_GRAPHIC_BASE(idx), addr);  in mxr_reg_graph_buffer()
228 	mxr_vsync_set_update(mdev, MXR_ENABLE);  in mxr_reg_graph_buffer()
229 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_graph_buffer()
232 void mxr_reg_vp_buffer(struct mxr_device *mdev,  in mxr_reg_vp_buffer()  argument
238 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_vp_buffer()
239 	mxr_vsync_set_update(mdev, MXR_DISABLE);  in mxr_reg_vp_buffer()
241 	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VP_ENABLE);  in mxr_reg_vp_buffer()
242 	vp_write_mask(mdev, VP_ENABLE, val, VP_ENABLE_ON);  in mxr_reg_vp_buffer()
244 	vp_write(mdev, VP_TOP_Y_PTR, luma_addr[0]);  in mxr_reg_vp_buffer()
245 	vp_write(mdev, VP_TOP_C_PTR, chroma_addr[0]);  in mxr_reg_vp_buffer()
246 	vp_write(mdev, VP_BOT_Y_PTR, luma_addr[1]);  in mxr_reg_vp_buffer()
247 	vp_write(mdev, VP_BOT_C_PTR, chroma_addr[1]);  in mxr_reg_vp_buffer()
249 	mxr_vsync_set_update(mdev, MXR_ENABLE);  in mxr_reg_vp_buffer()
250 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_vp_buffer()
290 	struct mxr_device *mdev = dev_data;  in mxr_irq_handler()  local
293 	spin_lock(&mdev->reg_slock);  in mxr_irq_handler()
294 	val = mxr_read(mdev, MXR_INT_STATUS);  in mxr_irq_handler()
298 		set_bit(MXR_EVENT_VSYNC, &mdev->event_flags);  in mxr_irq_handler()
300 		if (~mxr_read(mdev, MXR_CFG) & MXR_CFG_SCAN_PROGRASSIVE)  in mxr_irq_handler()
301 			change_bit(MXR_EVENT_TOP, &mdev->event_flags);  in mxr_irq_handler()
302 		wake_up(&mdev->event_queue);  in mxr_irq_handler()
309 	mxr_write(mdev, MXR_INT_STATUS, val);  in mxr_irq_handler()
311 	spin_unlock(&mdev->reg_slock);  in mxr_irq_handler()
316 	if (!test_bit(MXR_EVENT_TOP, &mdev->event_flags))  in mxr_irq_handler()
319 		mxr_irq_layer_handle(mdev->layer[i]);  in mxr_irq_handler()
323 void mxr_reg_s_output(struct mxr_device *mdev, int cookie)  in mxr_reg_s_output()  argument
328 	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_DST_MASK);  in mxr_reg_s_output()
331 void mxr_reg_streamon(struct mxr_device *mdev)  in mxr_reg_streamon()  argument
335 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_streamon()
339 	mxr_write_mask(mdev, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);  in mxr_reg_streamon()
340 	set_bit(MXR_EVENT_TOP, &mdev->event_flags);  in mxr_reg_streamon()
342 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_streamon()
345 void mxr_reg_streamoff(struct mxr_device *mdev)  in mxr_reg_streamoff()  argument
349 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_streamoff()
353 	mxr_write_mask(mdev, MXR_STATUS, 0, MXR_STATUS_REG_RUN);  in mxr_reg_streamoff()
355 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_streamoff()
358 int mxr_reg_wait4vsync(struct mxr_device *mdev)  in mxr_reg_wait4vsync()  argument
362 	clear_bit(MXR_EVENT_VSYNC, &mdev->event_flags);  in mxr_reg_wait4vsync()
364 	time_left = wait_event_timeout(mdev->event_queue,  in mxr_reg_wait4vsync()
365 			test_bit(MXR_EVENT_VSYNC, &mdev->event_flags),  in mxr_reg_wait4vsync()
369 	mxr_warn(mdev, "no vsync detected - timeout\n");  in mxr_reg_wait4vsync()
373 void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,  in mxr_reg_set_mbus_fmt()  argument
379 	spin_lock_irqsave(&mdev->reg_slock, flags);  in mxr_reg_set_mbus_fmt()
380 	mxr_vsync_set_update(mdev, MXR_DISABLE);  in mxr_reg_set_mbus_fmt()
406 	mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |  in mxr_reg_set_mbus_fmt()
410 	vp_write_mask(mdev, VP_MODE, val,  in mxr_reg_set_mbus_fmt()
413 	mxr_vsync_set_update(mdev, MXR_ENABLE);  in mxr_reg_set_mbus_fmt()
414 	spin_unlock_irqrestore(&mdev->reg_slock, flags);  in mxr_reg_set_mbus_fmt()
417 void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en)  in mxr_reg_graph_layer_stream()  argument
422 void mxr_reg_vp_layer_stream(struct mxr_device *mdev, int en)  in mxr_reg_vp_layer_stream()  argument
456 static inline void mxr_reg_vp_filter_set(struct mxr_device *mdev,  in mxr_reg_vp_filter_set()  argument
464 		vp_write(mdev, reg_id, val);  in mxr_reg_vp_filter_set()
468 static void mxr_reg_vp_default_filter(struct mxr_device *mdev)  in mxr_reg_vp_default_filter()  argument
470 	mxr_reg_vp_filter_set(mdev, VP_POLY8_Y0_LL,  in mxr_reg_vp_default_filter()
472 	mxr_reg_vp_filter_set(mdev, VP_POLY4_Y0_LL,  in mxr_reg_vp_default_filter()
474 	mxr_reg_vp_filter_set(mdev, VP_POLY4_C0_LL,  in mxr_reg_vp_default_filter()
478 static void mxr_reg_mxr_dump(struct mxr_device *mdev)  in mxr_reg_mxr_dump()  argument
482 	mxr_dbg(mdev, #reg_id " = %08x\n", \  in mxr_reg_mxr_dump()
483 		(u32)readl(mdev->res.mxr_regs + reg_id)); \  in mxr_reg_mxr_dump()
510 static void mxr_reg_vp_dump(struct mxr_device *mdev)  in mxr_reg_vp_dump()  argument
514 	mxr_dbg(mdev, #reg_id " = %08x\n", \  in mxr_reg_vp_dump()
515 		(u32) readl(mdev->res.vp_regs + reg_id)); \  in mxr_reg_vp_dump()
546 void mxr_reg_dump(struct mxr_device *mdev)  in mxr_reg_dump()  argument
548 	mxr_reg_mxr_dump(mdev);  in mxr_reg_dump()
549 	mxr_reg_vp_dump(mdev);  in mxr_reg_dump()