26 	cfg = readl(dev->regs + FIMC_REG_CISRCFMT);  in fimc_hw_reset()
31 	cfg = readl(dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_reset()
36 	cfg = readl(dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_reset()
79 	cfg = readl(dev->regs + FIMC_REG_CITRGFMT);  in fimc_hw_set_rotation()
100 		flip = readl(dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_set_rotation()
116 	cfg = readl(dev->regs + FIMC_REG_CITRGFMT);  in fimc_hw_set_target_format()
144 	cfg = readl(dev->regs + FIMC_REG_CITAREA);  in fimc_hw_set_target_format()
160 	cfg = readl(dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_set_out_dma_size()
190 	cfg = readl(dev->regs + FIMC_REG_CIOCTRL);  in fimc_hw_set_out_dma()
216 	u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE);  in fimc_hw_en_autoload()
226 	u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);  in fimc_hw_en_lastirq()
257 	u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_set_scaler()
326 	cfg = readl(dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_set_mainscaler()
335 		cfg = readl(dev->regs + FIMC_REG_CIEXTEN);  in fimc_hw_set_mainscaler()
354 	cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);  in fimc_hw_enable_capture()
368 	u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);  in fimc_hw_disable_capture()
400 	cfg = readl(dev->regs + FIMC_REG_CIOCTRL);  in fimc_hw_set_rgb_alpha()
447 	cfg = readl(dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_set_in_dma()
493 	cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM);  in fimc_hw_set_in_dma()
510 	u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_set_input_path()
525 	u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_set_output_path()
534 	u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);  in fimc_hw_set_input_addr()
562 	u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);  in fimc_hw_set_camera_polarity()
653 	u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST);  in fimc_hw_set_camera_offset()
675 	cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);  in fimc_hw_set_camera_type()
736 	u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_clear_irq()
743 	u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_enable_scaler()
753 	u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_activate_input_dma()
767 		reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3f;  in fimc_hw_get_frame_index()
771 	reg = readl(dev->regs + FIMC_REG_CISTATUS);  in fimc_hw_get_frame_index()
785 	reg = readl(dev->regs + FIMC_REG_CISTATUS2);  in fimc_hw_get_prev_frame_index()