20 void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr)  in fimc_is_fw_clear_irq1()  argument
22 	mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1);  in fimc_is_fw_clear_irq1()
25 void fimc_is_fw_clear_irq2(struct fimc_is *is)  in fimc_is_fw_clear_irq2()  argument
27 	u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2);  in fimc_is_fw_clear_irq2()
28 	mcuctl_write(cfg, is, MCUCTL_REG_INTCR2);  in fimc_is_fw_clear_irq2()
31 void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is)  in fimc_is_hw_set_intgr0_gd0()  argument
33 	mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0);  in fimc_is_hw_set_intgr0_gd0()
36 int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is)  in fimc_is_hw_wait_intmsr0_intmsd0()  argument
42 		cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);  in fimc_is_hw_wait_intmsr0_intmsd0()
46 			dev_warn(&is->pdev->dev, "%s timeout\n",  in fimc_is_hw_wait_intmsr0_intmsd0()
56 int fimc_is_hw_set_param(struct fimc_is *is)  in fimc_is_hw_set_param()  argument
58 	struct chain_config *config = &is->config[is->config_index];  in fimc_is_hw_set_param()
59 	unsigned int param_count = __get_pending_param_count(is);  in fimc_is_hw_set_param()
61 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_set_param()
63 	mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_set_param()
64 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_set_param()
65 	mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2));  in fimc_is_hw_set_param()
67 	mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3));  in fimc_is_hw_set_param()
68 	mcuctl_write(config->p_region_index[0], is, MCUCTL_REG_ISSR(4));  in fimc_is_hw_set_param()
69 	mcuctl_write(config->p_region_index[1], is, MCUCTL_REG_ISSR(5));  in fimc_is_hw_set_param()
71 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_set_param()
75 static int __maybe_unused fimc_is_hw_set_tune(struct fimc_is *is)  in fimc_is_hw_set_tune()  argument
77 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_set_tune()
79 	mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_set_tune()
80 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_set_tune()
81 	mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2));  in fimc_is_hw_set_tune()
83 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_set_tune()
89 int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args)  in fimc_is_hw_get_params()  argument
96 	is->i2h_cmd.num_args = num_args;  in fimc_is_hw_get_params()
100 			is->i2h_cmd.args[i] = mcuctl_read(is,  in fimc_is_hw_get_params()
103 			is->i2h_cmd.args[i] = 0;  in fimc_is_hw_get_params()
108 void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask)  in fimc_is_hw_set_isp_buf_mask()  argument
111 		dev_err(&is->pdev->dev, "%s(): not enough buffers (mask %#x)\n",  in fimc_is_hw_set_isp_buf_mask()
116 	if (mcuctl_read(is, MCUCTL_REG_ISSR(23)) != 0)  in fimc_is_hw_set_isp_buf_mask()
117 		dev_dbg(&is->pdev->dev, "non-zero DMA buffer mask\n");  in fimc_is_hw_set_isp_buf_mask()
119 	mcuctl_write(mask, is, MCUCTL_REG_ISSR(23));  in fimc_is_hw_set_isp_buf_mask()
122 void fimc_is_hw_set_sensor_num(struct fimc_is *is)  in fimc_is_hw_set_sensor_num()  argument
124 	pr_debug("setting sensor index to: %d\n", is->sensor_index);  in fimc_is_hw_set_sensor_num()
126 	mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_set_sensor_num()
127 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_set_sensor_num()
128 	mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2));  in fimc_is_hw_set_sensor_num()
129 	mcuctl_write(FIMC_IS_SENSORS_NUM, is, MCUCTL_REG_ISSR(3));  in fimc_is_hw_set_sensor_num()
132 void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index)  in fimc_is_hw_close_sensor()  argument
134 	if (is->sensor_index != index)  in fimc_is_hw_close_sensor()
137 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_close_sensor()
138 	mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_close_sensor()
139 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_close_sensor()
140 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2));  in fimc_is_hw_close_sensor()
141 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_close_sensor()
144 void fimc_is_hw_get_setfile_addr(struct fimc_is *is)  in fimc_is_hw_get_setfile_addr()  argument
146 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_get_setfile_addr()
147 	mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_get_setfile_addr()
148 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_get_setfile_addr()
149 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_get_setfile_addr()
152 void fimc_is_hw_load_setfile(struct fimc_is *is)  in fimc_is_hw_load_setfile()  argument
154 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_load_setfile()
155 	mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_load_setfile()
156 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_load_setfile()
157 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_load_setfile()
160 int fimc_is_hw_change_mode(struct fimc_is *is)  in fimc_is_hw_change_mode()  argument
167 	if (WARN_ON(is->config_index >= ARRAY_SIZE(cmd)))  in fimc_is_hw_change_mode()
170 	mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_change_mode()
171 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_change_mode()
172 	mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2));  in fimc_is_hw_change_mode()
173 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_change_mode()
177 void fimc_is_hw_stream_on(struct fimc_is *is)  in fimc_is_hw_stream_on()  argument
179 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_stream_on()
180 	mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_stream_on()
181 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_stream_on()
182 	mcuctl_write(0, is, MCUCTL_REG_ISSR(2));  in fimc_is_hw_stream_on()
183 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_stream_on()
186 void fimc_is_hw_stream_off(struct fimc_is *is)  in fimc_is_hw_stream_off()  argument
188 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_stream_off()
189 	mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_stream_off()
190 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_stream_off()
191 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_stream_off()
194 void fimc_is_hw_subip_power_off(struct fimc_is *is)  in fimc_is_hw_subip_power_off()  argument
196 	fimc_is_hw_wait_intmsr0_intmsd0(is);  in fimc_is_hw_subip_power_off()
197 	mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0));  in fimc_is_hw_subip_power_off()
198 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));  in fimc_is_hw_subip_power_off()
199 	fimc_is_hw_set_intgr0_gd0(is);  in fimc_is_hw_subip_power_off()
202 int fimc_is_itf_s_param(struct fimc_is *is, bool update)  in fimc_is_itf_s_param()  argument
207 		__is_hw_update_params(is);  in fimc_is_itf_s_param()
211 	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);  in fimc_is_itf_s_param()
212 	fimc_is_hw_set_param(is);  in fimc_is_itf_s_param()
213 	ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1,  in fimc_is_itf_s_param()
216 		dev_err(&is->pdev->dev, "%s() timeout\n", __func__);  in fimc_is_itf_s_param()
221 int fimc_is_itf_mode_change(struct fimc_is *is)  in fimc_is_itf_mode_change()  argument
225 	clear_bit(IS_ST_CHANGE_MODE, &is->state);  in fimc_is_itf_mode_change()
226 	fimc_is_hw_change_mode(is);  in fimc_is_itf_mode_change()
227 	ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1,  in fimc_is_itf_mode_change()
230 		dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n",  in fimc_is_itf_mode_change()
231 			__func__, is->config_index);  in fimc_is_itf_mode_change()