Lines Matching refs:VPIF_INTEN_SET
43 #define VPIF_INTEN_SET (0x0024) macro
297 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); in channel0_intr_enable()
300 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), in channel0_intr_enable()
301 VPIF_INTEN_SET); in channel0_intr_enable()
304 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), in channel0_intr_enable()
305 VPIF_INTEN_SET); in channel0_intr_enable()
319 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); in channel1_intr_enable()
322 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), in channel1_intr_enable()
323 VPIF_INTEN_SET); in channel1_intr_enable()
326 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), in channel1_intr_enable()
327 VPIF_INTEN_SET); in channel1_intr_enable()
458 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); in channel2_intr_enable()
460 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), in channel2_intr_enable()
461 VPIF_INTEN_SET); in channel2_intr_enable()
464 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), in channel2_intr_enable()
465 VPIF_INTEN_SET); in channel2_intr_enable()
479 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); in channel3_intr_enable()
482 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), in channel3_intr_enable()
483 VPIF_INTEN_SET); in channel3_intr_enable()
486 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), in channel3_intr_enable()
487 VPIF_INTEN_SET); in channel3_intr_enable()