Lines Matching refs:ar_outl
60 #define ar_outl(val, addr) outl((unsigned long)(val), (unsigned long)(addr)) macro
167 ar_outl(addr, PLDI2CDATA); in iic()
171 ar_outl(1, PLDI2CCND); in iic()
175 ar_outl(data1, PLDI2CDATA); in iic()
177 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); in iic()
181 ar_outl(data2, PLDI2CDATA); in iic()
183 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); in iic()
188 ar_outl(data3, PLDI2CDATA); in iic()
190 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); in iic()
197 ar_outl(2, PLDI2CCND); in iic()
198 ar_outl(2, PLDI2CCND); in iic()
213 ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */ in init_iic()
214 ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */ in init_iic()
215 ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */ in init_iic()
220 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */ in init_iic()
222 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */ in init_iic()
224 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */ in init_iic()
225 ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */ in init_iic()
236 ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */ in disable_dma()
241 ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */ in enable_dma()
246 ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */ in clear_dma_status()
296 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL); in ar_read()
297 ar_outl(0x01000000, M32R_DMA0CR1_PORTL); in ar_read()
300 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); in ar_read()
301 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); in ar_read()
302 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */ in ar_read()
303 ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */ in ar_read()
304 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */ in ar_read()
305 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */ in ar_read()
311 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); in ar_read()
322 ar_outl(arvcr1, ARVCR1); in ar_read()
324 ar_outl(0x8000, M32R_DMAEDET_PORTL); in ar_read()
325 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); in ar_read()
326 ar_outl(0x01000000, M32R_DMA0CR1_PORTL); in ar_read()
327 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL); in ar_read()
328 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL); in ar_read()
329 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); in ar_read()
330 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); in ar_read()
342 ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL); in ar_read()
348 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); in ar_read()
353 ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL); in ar_read()
359 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL); in ar_read()
552 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */ in ar_interrupt()
556 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL); in ar_interrupt()
578 ar_outl(arvcr1, ARVCR1); /* disable */ in ar_interrupt()
582 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); in ar_interrupt()
583 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL); in ar_interrupt()
610 ar_outl(0, ARVCR0); /* assert reset of AR LSI */ in ar_initialize()
613 ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */ in ar_initialize()
618 ar_outl(ARINTSEL_INT3, ARINTSEL); in ar_initialize()
624 ar_outl(cr, ARVCR1); in ar_initialize()