Lines Matching refs:SYSTEM_CONTROL_REG_BASE
41 #define SYSTEM_CONTROL_REG_BASE 0x0880 macro
80 #define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)
96 #define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04)
97 #define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08)
98 #define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C)
99 #define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10)
100 #define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14)
101 #define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18)
102 #define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C)
103 #define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20)
104 #define PCIE_IP_REG_ACS_ADDR (SYSTEM_CONTROL_REG_BASE + 0x24)
105 #define PCIE_IP_REG_ACS_DATA (SYSTEM_CONTROL_REG_BASE + 0x28)