126 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_pinnacle_init()
128 	mt352_write(fe, reset,          sizeof(reset));  in mt352_pinnacle_init()
129 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_pinnacle_init()
130 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_pinnacle_init()
131 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_pinnacle_init()
132 	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));  in mt352_pinnacle_init()
134 	mt352_write(fe, fsm_ctl_cfg,    sizeof(fsm_ctl_cfg));  in mt352_pinnacle_init()
135 	mt352_write(fe, scan_ctl_cfg,   sizeof(scan_ctl_cfg));  in mt352_pinnacle_init()
136 	mt352_write(fe, irq_cfg,        sizeof(irq_cfg));  in mt352_pinnacle_init()
149 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_aver777_init()
151 	mt352_write(fe, reset,          sizeof(reset));  in mt352_aver777_init()
152 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_aver777_init()
153 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_aver777_init()
154 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_aver777_init()
167 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_avermedia_xc3028_init()
169 	mt352_write(fe, reset,          sizeof(reset));  in mt352_avermedia_xc3028_init()
170 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_avermedia_xc3028_init()
171 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_avermedia_xc3028_init()
172 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_avermedia_xc3028_init()