Lines Matching refs:read_reg
437 write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER); in ivtv_dma_enc_start_xfer()
453 write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER); in ivtv_dma_dec_start_xfer()
556 if (read_reg(IVTV_REG_DMASTATUS) & 0x14) { in ivtv_irq_dma_read()
558 read_reg(IVTV_REG_DMASTATUS), in ivtv_irq_dma_read()
560 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_irq_dma_read()
623 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_irq_enc_dma_complete()
688 status = read_reg(IVTV_REG_DMASTATUS); in ivtv_irq_dma_err()
843 unsigned int frame = read_reg(IVTV_REG_DEC_LINE_FIELD) & 1; in ivtv_irq_vsync()
940 stat = read_reg(IVTV_REG_IRQSTATUS); in ivtv_irq_handler()
954 (read_reg(IVTV_REG_DEC_LINE_FIELD) & 1)) { in ivtv_irq_handler()
957 read_reg(IVTV_REG_DEC_LINE_FIELD) >> 16); in ivtv_irq_handler()
1083 IVTV_ERR("DMA TIMEOUT %08x %d\n", read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream); in ivtv_unfinished_dma()
1085 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_unfinished_dma()