Lines Matching refs:u32
201 u32 flags;
202 u32 cmd;
203 u32 retval;
204 u32 timeout;
205 u32 data[CX2341X_MBOX_MAX_DATA];
210 u32 data[CX2341X_MBOX_MAX_DATA]; /* last sent api data */
278 u32 src;
279 u32 dst;
280 u32 size;
314 u32 bytesused;
315 u32 readpos;
320 u32 buffers; /* number of buffers in this queue */
321 u32 length; /* total number of bytes of available buffer space */
322 u32 bytesused; /* total number of bytes used in this queue */
334 u32 caps; /* V4L2 capabilities */
340 u32 pending_offset;
341 u32 pending_backup;
344 u32 dma_offset;
345 u32 dma_backup;
350 u32 dma_last_offset;
353 u32 buffers;
354 u32 buf_size;
355 u32 buffers_stolen;
395 u32 update;
398 u32 src_w;
399 u32 src_h;
402 u32 dst_w;
403 u32 dst_h;
406 u32 vis_w;
407 u32 vis_h;
408 u32 interlaced_y;
409 u32 interlaced_uv;
411 u32 tru_w;
412 u32 tru_h;
413 u32 offset_y;
415 u32 sync_field;
416 u32 delay;
417 u32 interlaced;
433 u32 reg_2834;
434 u32 reg_2838;
435 u32 reg_283c;
436 u32 reg_2840;
437 u32 reg_2844;
438 u32 reg_2848;
439 u32 reg_2854;
440 u32 reg_285c;
441 u32 reg_2864;
443 u32 reg_2870;
444 u32 reg_2874;
445 u32 reg_2890;
446 u32 reg_2898;
447 u32 reg_289c;
449 u32 reg_2918;
450 u32 reg_291c;
451 u32 reg_2920;
452 u32 reg_2924;
453 u32 reg_2928;
454 u32 reg_292c;
455 u32 reg_2930;
457 u32 reg_2934;
459 u32 reg_2938;
460 u32 reg_293c;
461 u32 reg_2940;
462 u32 reg_2944;
463 u32 reg_2948;
464 u32 reg_294c;
465 u32 reg_2950;
466 u32 reg_2954;
467 u32 reg_2958;
468 u32 reg_295c;
469 u32 reg_2960;
470 u32 reg_2964;
471 u32 reg_2968;
472 u32 reg_296c;
474 u32 reg_2970;
482 u32 osd_x_offset;
483 u32 osd_y_offset;
485 u32 osd_x_pan;
486 u32 osd_y_pan;
488 u32 osd_vis_w;
489 u32 osd_vis_h;
491 u32 osd_full_w;
492 u32 osd_full_h;
503 u32 yuv_forced_update;
521 u32 v4l2_src_w;
522 u32 v4l2_src_h;
542 u32 raw_decoder_line_size; /* raw VBI line size from digitizer */
545 u32 sliced_decoder_line_size; /* sliced VBI line size from digitizer */
549 u32 start[2]; /* start of first VBI line in the odd/even fields */
550 u32 count; /* number of VBI lines per field */
551 u32 raw_size; /* size of raw VBI line from the digitizer */
552 u32 sliced_size; /* size of sliced VBI line from the digitizer */
554 u32 dec_start; /* start in decoder memory of VBI re-insertion buffers */
555 u32 enc_start; /* start in encoder memory of VBI capture buffers */
556 u32 enc_size; /* size of VBI capture area */
565 u32 frame; /* frame counter hack needed for backwards compatibility
600 u32 sliced_mpeg_size[IVTV_VBI_FRAMES];
602 u32 inserted_frame; /* index in sliced_mpeg_size of next sliced data
620 u32 v4l2_cap; /* V4L2 capabilities of card */
621 u32 hw_flags; /* hardware description of the board */
655 u32 audio_input; /* current audio input */
656 u32 active_input; /* current video input */
657 u32 active_output; /* current video output */
682 u32 irqmask; /* active interrupts */
683 u32 irq_rr_idx; /* round-robin stream index */
690 u32 dma_data_req_offset; /* store offset in decoder memory of current DMA request */
691 u32 dma_data_req_size; /* store size of current DMA request */
695 u32 last_vsync_field; /* last seen vsync field */
718 u32 pgm_info_offset; /* start of pgm info in encoder memory */
719 u32 pgm_info_num; /* number of elements in the pgm cyclic buffer in encoder memory */
720 …u32 pgm_info_write_idx; /* last index written by the card that was transferred to pgm_info…
721 u32 pgm_info_read_idx; /* last index in pgm_info read by the application */
726 u32 open_id; /* incremented each time an open occurs, is >= 1 */
732 u32 last_dec_timing[3]; /* cache last retrieved pts/scr/frame values */
734 u32 dualwatch_stereo_mode; /* current detected dualwatch stereo mode */
751 u32 osd_chroma_key; /* current chroma key */
772 void ivtv_set_irq_mask(struct ivtv *itv, u32 mask);
773 void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask);
817 #define read_enc(addr) readl(itv->enc_mem + (u32)(addr))
818 #define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr))
822 #define read_dec(addr) readl(itv->dec_mem + (u32)(addr))
823 #define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr))