254 static int netup_fpga_op_rw(struct fpga_internal *inter, int addr,  in netup_fpga_op_rw()  function
277 	netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0);  in altera_ci_op_cam()
278 	netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0);  in altera_ci_op_cam()
279 	store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);  in altera_ci_op_cam()
284 	netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0);  in altera_ci_op_cam()
285 	mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read);  in altera_ci_op_cam()
337 	ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);  in altera_ci_slot_reset()
338 	netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,  in altera_ci_slot_reset()
348 		ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,  in altera_ci_slot_reset()
384 	ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);  in altera_ci_slot_ts_ctl()
385 	netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,  in altera_ci_slot_ts_ctl()
404 	ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD);  in netup_read_ci_status()
405 	ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);  in netup_read_ci_status()
531 	netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0);  in altera_pid_control()
532 	netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,  in altera_pid_control()
535 	store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD);  in altera_pid_control()
542 	netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0);  in altera_pid_control()
568 		netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0);  in altera_toggle_fullts_streaming()
570 		netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,  in altera_toggle_fullts_streaming()
573 		netup_fpga_op_rw(inter, NETUP_CI_PID_DATA,  in altera_toggle_fullts_streaming()
776 	netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0);  in altera_ci_init()
777 	netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0);  in altera_ci_init()
780 	store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);  in altera_ci_init()
782 	netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);  in altera_ci_init()
784 	ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD);  in altera_ci_init()
786 	netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0);  in altera_ci_init()
822 	store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);  in altera_ci_tuner_reset()
824 	netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);  in altera_ci_tuner_reset()
827 	netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);  in altera_ci_tuner_reset()