Lines Matching refs:cx18_write_reg_expect
216 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, in cx18_halt_firmware()
218 cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL, in cx18_halt_firmware()
229 cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL, in cx18_init_power()
309 cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1, in cx18_init_power()
311 cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2, in cx18_init_power()
315 cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1, in cx18_init_power()
317 cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2, in cx18_init_power()
321 cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1, in cx18_init_power()
323 cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2, in cx18_init_power()
325 cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1, in cx18_init_power()
327 cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2, in cx18_init_power()
334 cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET, in cx18_init_memory()
354 cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET, in cx18_init_memory()
361 cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN, in cx18_init_memory()
392 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, in cx18_firmware_init()
420 cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET, in cx18_firmware_init()
454 cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400); in cx18_firmware_init()