Lines Matching refs:sd
100 struct v4l2_subdev sd; member
253 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) in to_state() argument
255 return container_of(sd, struct adv7842_state, sd); in to_state()
260 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; in to_sd()
368 static inline int io_read(struct v4l2_subdev *sd, u8 reg) in io_read() argument
370 struct i2c_client *client = v4l2_get_subdevdata(sd); in io_read()
375 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) in io_write() argument
377 struct i2c_client *client = v4l2_get_subdevdata(sd); in io_write()
382 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in io_write_and_or() argument
384 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); in io_write_and_or()
387 static inline int io_write_clr_set(struct v4l2_subdev *sd, in io_write_clr_set() argument
390 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); in io_write_clr_set()
393 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) in avlink_read() argument
395 struct adv7842_state *state = to_state(sd); in avlink_read()
400 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) in avlink_write() argument
402 struct adv7842_state *state = to_state(sd); in avlink_write()
407 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) in cec_read() argument
409 struct adv7842_state *state = to_state(sd); in cec_read()
414 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) in cec_write() argument
416 struct adv7842_state *state = to_state(sd); in cec_write()
421 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in cec_write_and_or() argument
423 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); in cec_write_and_or()
426 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) in infoframe_read() argument
428 struct adv7842_state *state = to_state(sd); in infoframe_read()
433 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) in infoframe_write() argument
435 struct adv7842_state *state = to_state(sd); in infoframe_write()
440 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) in sdp_io_read() argument
442 struct adv7842_state *state = to_state(sd); in sdp_io_read()
447 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) in sdp_io_write() argument
449 struct adv7842_state *state = to_state(sd); in sdp_io_write()
454 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in sdp_io_write_and_or() argument
456 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); in sdp_io_write_and_or()
459 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) in sdp_read() argument
461 struct adv7842_state *state = to_state(sd); in sdp_read()
466 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in sdp_write() argument
468 struct adv7842_state *state = to_state(sd); in sdp_write()
473 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in sdp_write_and_or() argument
475 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); in sdp_write_and_or()
478 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) in afe_read() argument
480 struct adv7842_state *state = to_state(sd); in afe_read()
485 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) in afe_write() argument
487 struct adv7842_state *state = to_state(sd); in afe_write()
492 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in afe_write_and_or() argument
494 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); in afe_write_and_or()
497 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) in rep_read() argument
499 struct adv7842_state *state = to_state(sd); in rep_read()
504 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) in rep_write() argument
506 struct adv7842_state *state = to_state(sd); in rep_write()
511 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in rep_write_and_or() argument
513 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); in rep_write_and_or()
516 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) in edid_read() argument
518 struct adv7842_state *state = to_state(sd); in edid_read()
523 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) in edid_write() argument
525 struct adv7842_state *state = to_state(sd); in edid_write()
530 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) in hdmi_read() argument
532 struct adv7842_state *state = to_state(sd); in hdmi_read()
537 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) in hdmi_write() argument
539 struct adv7842_state *state = to_state(sd); in hdmi_write()
544 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in hdmi_write_and_or() argument
546 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); in hdmi_write_and_or()
549 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) in cp_read() argument
551 struct adv7842_state *state = to_state(sd); in cp_read()
556 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in cp_write() argument
558 struct adv7842_state *state = to_state(sd); in cp_write()
563 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in cp_write_and_or() argument
565 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); in cp_write_and_or()
568 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) in vdp_read() argument
570 struct adv7842_state *state = to_state(sd); in vdp_read()
575 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in vdp_write() argument
577 struct adv7842_state *state = to_state(sd); in vdp_write()
582 static void main_reset(struct v4l2_subdev *sd) in main_reset() argument
584 struct i2c_client *client = v4l2_get_subdevdata(sd); in main_reset()
586 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in main_reset()
653 static inline bool is_analog_input(struct v4l2_subdev *sd) in is_analog_input() argument
655 struct adv7842_state *state = to_state(sd); in is_analog_input()
661 static inline bool is_digital_input(struct v4l2_subdev *sd) in is_digital_input() argument
663 struct adv7842_state *state = to_state(sd); in is_digital_input()
691 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) in adv7842_get_dv_timings_cap() argument
693 return is_digital_input(sd) ? &adv7842_timings_cap_digital : in adv7842_get_dv_timings_cap()
704 struct v4l2_subdev *sd = &state->sd; in adv7842_delayed_work_enable_hotplug() local
708 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", in adv7842_delayed_work_enable_hotplug()
715 io_write_and_or(sd, 0x20, 0xcf, mask); in adv7842_delayed_work_enable_hotplug()
718 static int edid_write_vga_segment(struct v4l2_subdev *sd) in edid_write_vga_segment() argument
720 struct i2c_client *client = v4l2_get_subdevdata(sd); in edid_write_vga_segment()
721 struct adv7842_state *state = to_state(sd); in edid_write_vga_segment()
726 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); in edid_write_vga_segment()
729 io_write_and_or(sd, 0x20, 0xcf, 0x00); in edid_write_vga_segment()
732 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); in edid_write_vga_segment()
735 rep_write_and_or(sd, 0x77, 0xef, 0x10); in edid_write_vga_segment()
746 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); in edid_write_vga_segment()
749 if (rep_read(sd, 0x79) & 0x20) in edid_write_vga_segment()
798 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) in edid_write_hdmi_segment() argument
800 struct i2c_client *client = v4l2_get_subdevdata(sd); in edid_write_hdmi_segment()
801 struct adv7842_state *state = to_state(sd); in edid_write_hdmi_segment()
807 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n", in edid_write_hdmi_segment()
811 io_write_and_or(sd, 0x20, 0xcf, 0x00); in edid_write_hdmi_segment()
814 rep_write_and_or(sd, 0x77, 0xf3, 0x00); in edid_write_hdmi_segment()
820 rep_write_and_or(sd, 0x77, 0xef, 0x00); in edid_write_hdmi_segment()
832 rep_write(sd, 0x72, val[spa_loc]); in edid_write_hdmi_segment()
833 rep_write(sd, 0x73, val[spa_loc + 1]); in edid_write_hdmi_segment()
835 rep_write(sd, 0x74, val[spa_loc]); in edid_write_hdmi_segment()
836 rep_write(sd, 0x75, val[spa_loc + 1]); in edid_write_hdmi_segment()
838 rep_write(sd, 0x76, spa_loc & 0xff); in edid_write_hdmi_segment()
839 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); in edid_write_hdmi_segment()
844 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); in edid_write_hdmi_segment()
847 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) in edid_write_hdmi_segment()
867 static void adv7842_inv_register(struct v4l2_subdev *sd) in adv7842_inv_register() argument
869 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); in adv7842_inv_register()
870 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); in adv7842_inv_register()
871 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); in adv7842_inv_register()
872 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); in adv7842_inv_register()
873 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); in adv7842_inv_register()
874 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); in adv7842_inv_register()
875 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); in adv7842_inv_register()
876 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); in adv7842_inv_register()
877 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); in adv7842_inv_register()
878 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); in adv7842_inv_register()
879 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); in adv7842_inv_register()
880 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); in adv7842_inv_register()
883 static int adv7842_g_register(struct v4l2_subdev *sd, in adv7842_g_register() argument
889 reg->val = io_read(sd, reg->reg & 0xff); in adv7842_g_register()
892 reg->val = avlink_read(sd, reg->reg & 0xff); in adv7842_g_register()
895 reg->val = cec_read(sd, reg->reg & 0xff); in adv7842_g_register()
898 reg->val = infoframe_read(sd, reg->reg & 0xff); in adv7842_g_register()
901 reg->val = sdp_io_read(sd, reg->reg & 0xff); in adv7842_g_register()
904 reg->val = sdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
907 reg->val = afe_read(sd, reg->reg & 0xff); in adv7842_g_register()
910 reg->val = rep_read(sd, reg->reg & 0xff); in adv7842_g_register()
913 reg->val = edid_read(sd, reg->reg & 0xff); in adv7842_g_register()
916 reg->val = hdmi_read(sd, reg->reg & 0xff); in adv7842_g_register()
919 reg->val = cp_read(sd, reg->reg & 0xff); in adv7842_g_register()
922 reg->val = vdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
925 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv7842_g_register()
926 adv7842_inv_register(sd); in adv7842_g_register()
932 static int adv7842_s_register(struct v4l2_subdev *sd, in adv7842_s_register() argument
939 io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
942 avlink_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
945 cec_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
948 infoframe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
951 sdp_io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
954 sdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
957 afe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
960 rep_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
963 edid_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
966 hdmi_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
969 cp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
972 vdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
975 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv7842_s_register()
976 adv7842_inv_register(sd); in adv7842_s_register()
983 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) in adv7842_s_detect_tx_5v_ctrl() argument
985 struct adv7842_state *state = to_state(sd); in adv7842_s_detect_tx_5v_ctrl()
987 u8 reg_io_6f = io_read(sd, 0x6f); in adv7842_s_detect_tx_5v_ctrl()
995 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val); in adv7842_s_detect_tx_5v_ctrl()
1002 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, in find_and_set_predefined_video_timings() argument
1011 is_digital_input(sd) ? 250000 : 1000000)) in find_and_set_predefined_video_timings()
1014 io_write(sd, 0x00, predef_vid_timings[i].vid_std); in find_and_set_predefined_video_timings()
1016 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); in find_and_set_predefined_video_timings()
1023 static int configure_predefined_video_timings(struct v4l2_subdev *sd, in configure_predefined_video_timings() argument
1026 struct adv7842_state *state = to_state(sd); in configure_predefined_video_timings()
1029 v4l2_dbg(1, debug, sd, "%s\n", __func__); in configure_predefined_video_timings()
1032 io_write(sd, 0x16, 0x43); in configure_predefined_video_timings()
1033 io_write(sd, 0x17, 0x5a); in configure_predefined_video_timings()
1035 cp_write_and_or(sd, 0x81, 0xef, 0x00); in configure_predefined_video_timings()
1036 cp_write(sd, 0x26, 0x00); in configure_predefined_video_timings()
1037 cp_write(sd, 0x27, 0x00); in configure_predefined_video_timings()
1038 cp_write(sd, 0x28, 0x00); in configure_predefined_video_timings()
1039 cp_write(sd, 0x29, 0x00); in configure_predefined_video_timings()
1040 cp_write(sd, 0x8f, 0x40); in configure_predefined_video_timings()
1041 cp_write(sd, 0x90, 0x00); in configure_predefined_video_timings()
1042 cp_write(sd, 0xa5, 0x00); in configure_predefined_video_timings()
1043 cp_write(sd, 0xa6, 0x00); in configure_predefined_video_timings()
1044 cp_write(sd, 0xa7, 0x00); in configure_predefined_video_timings()
1045 cp_write(sd, 0xab, 0x00); in configure_predefined_video_timings()
1046 cp_write(sd, 0xac, 0x00); in configure_predefined_video_timings()
1051 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
1054 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
1058 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
1061 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
1065 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in configure_predefined_video_timings()
1075 static void configure_custom_video_timings(struct v4l2_subdev *sd, in configure_custom_video_timings() argument
1078 struct adv7842_state *state = to_state(sd); in configure_custom_video_timings()
1079 struct i2c_client *client = v4l2_get_subdevdata(sd); in configure_custom_video_timings()
1093 v4l2_dbg(2, debug, sd, "%s\n", __func__); in configure_custom_video_timings()
1099 io_write(sd, 0x00, 0x07); /* video std */ in configure_custom_video_timings()
1100 io_write(sd, 0x01, 0x02); /* prim mode */ in configure_custom_video_timings()
1102 cp_write_and_or(sd, 0x81, 0xef, 0x10); in configure_custom_video_timings()
1108 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); in configure_custom_video_timings()
1113 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); in configure_custom_video_timings()
1114 cp_write(sd, 0x27, (cp_start_sav & 0xff)); in configure_custom_video_timings()
1115 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); in configure_custom_video_timings()
1116 cp_write(sd, 0x29, (cp_start_eav & 0xff)); in configure_custom_video_timings()
1119 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); in configure_custom_video_timings()
1120 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | in configure_custom_video_timings()
1122 cp_write(sd, 0xa7, cp_end_vbi & 0xff); in configure_custom_video_timings()
1127 io_write(sd, 0x00, 0x02); /* video std */ in configure_custom_video_timings()
1128 io_write(sd, 0x01, 0x06); /* prim mode */ in configure_custom_video_timings()
1131 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in configure_custom_video_timings()
1136 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); in configure_custom_video_timings()
1137 cp_write(sd, 0x90, ch1_fr_ll & 0xff); in configure_custom_video_timings()
1138 cp_write(sd, 0xab, (height >> 4) & 0xff); in configure_custom_video_timings()
1139 cp_write(sd, 0xac, (height & 0x0f) << 4); in configure_custom_video_timings()
1142 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b… in adv7842_set_offset() argument
1144 struct adv7842_state *state = to_state(sd); in adv7842_set_offset()
1153 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv7842_set_offset()
1157 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); in adv7842_set_offset()
1164 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); in adv7842_set_offset()
1167 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 ga… in adv7842_set_gain() argument
1169 struct adv7842_state *state = to_state(sd); in adv7842_set_gain()
1182 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv7842_set_gain()
1193 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); in adv7842_set_gain()
1196 static void set_rgb_quantization_range(struct v4l2_subdev *sd) in set_rgb_quantization_range() argument
1198 struct adv7842_state *state = to_state(sd); in set_rgb_quantization_range()
1199 bool rgb_output = io_read(sd, 0x02) & 0x02; in set_rgb_quantization_range()
1200 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; in set_rgb_quantization_range()
1202 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", in set_rgb_quantization_range()
1206 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1207 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1214 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1221 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in set_rgb_quantization_range()
1228 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in set_rgb_quantization_range()
1237 io_write_and_or(sd, 0x02, 0x0f, 0x00); in set_rgb_quantization_range()
1240 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1242 if (is_digital_input(sd) && rgb_output) { in set_rgb_quantization_range()
1243 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1245 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1246 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1253 io_write_and_or(sd, 0x02, 0x0f, 0x20); in set_rgb_quantization_range()
1258 io_write_and_or(sd, 0x02, 0x0f, 0x00); in set_rgb_quantization_range()
1264 io_write_and_or(sd, 0x02, 0x0f, 0x60); in set_rgb_quantization_range()
1269 io_write_and_or(sd, 0x02, 0x0f, 0x10); in set_rgb_quantization_range()
1271 if (is_analog_input(sd) || hdmi_signal) in set_rgb_quantization_range()
1276 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1278 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1279 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1287 struct v4l2_subdev *sd = to_sd(ctrl); in adv7842_s_ctrl() local
1288 struct adv7842_state *state = to_state(sd); in adv7842_s_ctrl()
1297 cp_write(sd, 0x3c, ctrl->val); in adv7842_s_ctrl()
1298 sdp_write(sd, 0x14, ctrl->val); in adv7842_s_ctrl()
1302 cp_write(sd, 0x3a, ctrl->val); in adv7842_s_ctrl()
1303 sdp_write(sd, 0x13, ctrl->val); in adv7842_s_ctrl()
1307 cp_write(sd, 0x3b, ctrl->val); in adv7842_s_ctrl()
1308 sdp_write(sd, 0x15, ctrl->val); in adv7842_s_ctrl()
1312 cp_write(sd, 0x3d, ctrl->val); in adv7842_s_ctrl()
1313 sdp_write(sd, 0x16, ctrl->val); in adv7842_s_ctrl()
1318 afe_write(sd, 0xc8, ctrl->val); in adv7842_s_ctrl()
1321 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1322 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1342 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); in adv7842_s_ctrl()
1343 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); in adv7842_s_ctrl()
1346 cp_write(sd, 0xc1, R); in adv7842_s_ctrl()
1347 cp_write(sd, 0xc0, G); in adv7842_s_ctrl()
1348 cp_write(sd, 0xc2, B); in adv7842_s_ctrl()
1350 sdp_write(sd, 0xde, Y); in adv7842_s_ctrl()
1351 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); in adv7842_s_ctrl()
1356 set_rgb_quantization_range(sd); in adv7842_s_ctrl()
1362 static inline bool no_power(struct v4l2_subdev *sd) in no_power() argument
1364 return io_read(sd, 0x0c) & 0x24; in no_power()
1367 static inline bool no_cp_signal(struct v4l2_subdev *sd) in no_cp_signal() argument
1369 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); in no_cp_signal()
1372 static inline bool is_hdmi(struct v4l2_subdev *sd) in is_hdmi() argument
1374 return hdmi_read(sd, 0x05) & 0x80; in is_hdmi()
1377 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) in adv7842_g_input_status() argument
1379 struct adv7842_state *state = to_state(sd); in adv7842_g_input_status()
1383 if (io_read(sd, 0x0c) & 0x24) in adv7842_g_input_status()
1388 if (!(sdp_read(sd, 0x5A) & 0x01)) in adv7842_g_input_status()
1391 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", in adv7842_g_input_status()
1396 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || in adv7842_g_input_status()
1397 !(cp_read(sd, 0xb1) & 0x80)) in adv7842_g_input_status()
1401 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) in adv7842_g_input_status()
1404 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", in adv7842_g_input_status()
1416 static int stdi2dv_timings(struct v4l2_subdev *sd, in stdi2dv_timings() argument
1420 struct adv7842_state *state = to_state(sd); in stdi2dv_timings()
1429 adv7842_get_dv_timings_cap(sd), in stdi2dv_timings()
1457 v4l2_dbg(2, debug, sd, in stdi2dv_timings()
1464 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) in read_stdi() argument
1468 adv7842_g_input_status(sd, &status); in read_stdi()
1470 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); in read_stdi()
1474 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); in read_stdi()
1475 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); in read_stdi()
1476 stdi->lcvs = cp_read(sd, 0xb3) >> 3; in read_stdi()
1478 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { in read_stdi()
1479 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? in read_stdi()
1480 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in read_stdi()
1481 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? in read_stdi()
1482 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in read_stdi()
1487 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; in read_stdi()
1490 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); in read_stdi()
1494 v4l2_dbg(2, debug, sd, in read_stdi()
1503 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, in adv7842_enum_dv_timings() argument
1510 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); in adv7842_enum_dv_timings()
1513 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, in adv7842_dv_timings_cap() argument
1519 *cap = *adv7842_get_dv_timings_cap(sd); in adv7842_dv_timings_cap()
1525 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, in adv7842_fill_optional_dv_timings_fields() argument
1528 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), in adv7842_fill_optional_dv_timings_fields()
1529 is_digital_input(sd) ? 250000 : 1000000, in adv7842_fill_optional_dv_timings_fields()
1533 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, in adv7842_query_dv_timings() argument
1536 struct adv7842_state *state = to_state(sd); in adv7842_query_dv_timings()
1540 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_query_dv_timings()
1549 if (read_stdi(sd, &stdi)) { in adv7842_query_dv_timings()
1551 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); in adv7842_query_dv_timings()
1559 if (is_digital_input(sd)) { in adv7842_query_dv_timings()
1564 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); in adv7842_query_dv_timings()
1565 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); in adv7842_query_dv_timings()
1566 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; in adv7842_query_dv_timings()
1567 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); in adv7842_query_dv_timings()
1568 if (is_hdmi(sd)) { in adv7842_query_dv_timings()
1570 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); in adv7842_query_dv_timings()
1573 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + in adv7842_query_dv_timings()
1574 hdmi_read(sd, 0x21); in adv7842_query_dv_timings()
1575 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + in adv7842_query_dv_timings()
1576 hdmi_read(sd, 0x23); in adv7842_query_dv_timings()
1577 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + in adv7842_query_dv_timings()
1578 hdmi_read(sd, 0x25); in adv7842_query_dv_timings()
1579 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + in adv7842_query_dv_timings()
1580 hdmi_read(sd, 0x2b)) / 2; in adv7842_query_dv_timings()
1581 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + in adv7842_query_dv_timings()
1582 hdmi_read(sd, 0x2f)) / 2; in adv7842_query_dv_timings()
1583 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + in adv7842_query_dv_timings()
1584 hdmi_read(sd, 0x33)) / 2; in adv7842_query_dv_timings()
1585 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv7842_query_dv_timings()
1586 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); in adv7842_query_dv_timings()
1588 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + in adv7842_query_dv_timings()
1589 hdmi_read(sd, 0x0c); in adv7842_query_dv_timings()
1590 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + in adv7842_query_dv_timings()
1591 hdmi_read(sd, 0x2d)) / 2; in adv7842_query_dv_timings()
1592 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + in adv7842_query_dv_timings()
1593 hdmi_read(sd, 0x31)) / 2; in adv7842_query_dv_timings()
1594 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + in adv7842_query_dv_timings()
1595 hdmi_read(sd, 0x35)) / 2; in adv7842_query_dv_timings()
1601 adv7842_fill_optional_dv_timings_fields(sd, timings); in adv7842_query_dv_timings()
1607 if (!stdi2dv_timings(sd, &stdi, timings)) in adv7842_query_dv_timings()
1610 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); in adv7842_query_dv_timings()
1611 if (!stdi2dv_timings(sd, &stdi, timings)) in adv7842_query_dv_timings()
1614 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); in adv7842_query_dv_timings()
1615 if (stdi2dv_timings(sd, &stdi, timings)) { in adv7842_query_dv_timings()
1626 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); in adv7842_query_dv_timings()
1629 cp_write_and_or(sd, 0x86, 0xf9, 0x00); in adv7842_query_dv_timings()
1631 cp_write_and_or(sd, 0x86, 0xf9, 0x04); in adv7842_query_dv_timings()
1633 cp_write_and_or(sd, 0x86, 0xf9, 0x02); in adv7842_query_dv_timings()
1637 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); in adv7842_query_dv_timings()
1645 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", in adv7842_query_dv_timings()
1650 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, in adv7842_s_dv_timings() argument
1653 struct adv7842_state *state = to_state(sd); in adv7842_s_dv_timings()
1657 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_s_dv_timings()
1663 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); in adv7842_s_dv_timings()
1669 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), in adv7842_s_dv_timings()
1673 adv7842_fill_optional_dv_timings_fields(sd, timings); in adv7842_s_dv_timings()
1677 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); in adv7842_s_dv_timings()
1680 err = configure_predefined_video_timings(sd, timings); in adv7842_s_dv_timings()
1684 configure_custom_video_timings(sd, bt); in adv7842_s_dv_timings()
1687 set_rgb_quantization_range(sd); in adv7842_s_dv_timings()
1691 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", in adv7842_s_dv_timings()
1696 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, in adv7842_g_dv_timings() argument
1699 struct adv7842_state *state = to_state(sd); in adv7842_g_dv_timings()
1707 static void enable_input(struct v4l2_subdev *sd) in enable_input() argument
1709 struct adv7842_state *state = to_state(sd); in enable_input()
1711 set_rgb_quantization_range(sd); in enable_input()
1716 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ in enable_input()
1719 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ in enable_input()
1720 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ in enable_input()
1721 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ in enable_input()
1724 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in enable_input()
1730 static void disable_input(struct v4l2_subdev *sd) in disable_input() argument
1732 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ in disable_input()
1734 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ in disable_input()
1735 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ in disable_input()
1738 static void sdp_csc_coeff(struct v4l2_subdev *sd, in sdp_csc_coeff() argument
1742 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); in sdp_csc_coeff()
1748 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); in sdp_csc_coeff()
1751 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); in sdp_csc_coeff()
1752 sdp_io_write(sd, 0xe1, c->A1); in sdp_csc_coeff()
1753 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); in sdp_csc_coeff()
1754 sdp_io_write(sd, 0xe3, c->A2); in sdp_csc_coeff()
1755 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); in sdp_csc_coeff()
1756 sdp_io_write(sd, 0xe5, c->A3); in sdp_csc_coeff()
1759 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); in sdp_csc_coeff()
1760 sdp_io_write(sd, 0xe7, c->A4); in sdp_csc_coeff()
1763 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); in sdp_csc_coeff()
1764 sdp_io_write(sd, 0xe9, c->B1); in sdp_csc_coeff()
1765 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); in sdp_csc_coeff()
1766 sdp_io_write(sd, 0xeb, c->B2); in sdp_csc_coeff()
1767 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); in sdp_csc_coeff()
1768 sdp_io_write(sd, 0xed, c->B3); in sdp_csc_coeff()
1771 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); in sdp_csc_coeff()
1772 sdp_io_write(sd, 0xef, c->B4); in sdp_csc_coeff()
1775 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); in sdp_csc_coeff()
1776 sdp_io_write(sd, 0xf1, c->C1); in sdp_csc_coeff()
1777 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); in sdp_csc_coeff()
1778 sdp_io_write(sd, 0xf3, c->C2); in sdp_csc_coeff()
1779 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); in sdp_csc_coeff()
1780 sdp_io_write(sd, 0xf5, c->C3); in sdp_csc_coeff()
1783 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); in sdp_csc_coeff()
1784 sdp_io_write(sd, 0xf7, c->C4); in sdp_csc_coeff()
1787 static void select_input(struct v4l2_subdev *sd, in select_input() argument
1790 struct adv7842_state *state = to_state(sd); in select_input()
1794 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ in select_input()
1795 io_write(sd, 0x01, 0); /* prim mode */ in select_input()
1797 cp_write_and_or(sd, 0x81, 0xef, 0x10); in select_input()
1799 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1800 afe_write(sd, 0xc8, 0x00); /* phase control */ in select_input()
1802 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ in select_input()
1806 afe_write_and_or(sd, 0x02, 0x7f, 0x80); in select_input()
1808 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ in select_input()
1809 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ in select_input()
1811 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ in select_input()
1812 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ in select_input()
1814 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ in select_input()
1815 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ in select_input()
1817 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ in select_input()
1818 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ in select_input()
1821 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ in select_input()
1822 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ in select_input()
1824 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ in select_input()
1825 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ in select_input()
1826 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ in select_input()
1827 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ in select_input()
1828 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ in select_input()
1829 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ in select_input()
1830 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ in select_input()
1833 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); in select_input()
1840 afe_write_and_or(sd, 0x02, 0x7f, 0x00); in select_input()
1842 io_write(sd, 0x00, vid_std_select); /* video std */ in select_input()
1843 io_write(sd, 0x01, 0x02); /* prim mode */ in select_input()
1844 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs in select_input()
1847 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1848 afe_write(sd, 0xc8, 0x00); /* phase control */ in select_input()
1851 io_write_and_or(sd, 0x02, 0x0f, 0x60); in select_input()
1854 io_write_and_or(sd, 0x02, 0x0f, 0x10); in select_input()
1860 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ in select_input()
1861 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ in select_input()
1864 cp_write(sd, 0x73, 0x10); in select_input()
1865 cp_write(sd, 0x74, 0x04); in select_input()
1866 cp_write(sd, 0x75, 0x01); in select_input()
1867 cp_write(sd, 0x76, 0x00); in select_input()
1869 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ in select_input()
1870 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ in select_input()
1871 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ in select_input()
1876 afe_write_and_or(sd, 0x02, 0x7f, 0x00); in select_input()
1879 hdmi_write(sd, 0x00, 0x02); /* select port A */ in select_input()
1881 hdmi_write(sd, 0x00, 0x03); /* select port B */ in select_input()
1882 io_write(sd, 0x00, vid_std_select); /* video std */ in select_input()
1883 io_write(sd, 0x01, 5); /* prim mode */ in select_input()
1884 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs in select_input()
1890 hdmi_write(sd, 0xc0, 0x00); in select_input()
1891 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ in select_input()
1892 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ in select_input()
1893 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ in select_input()
1894 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ in select_input()
1895 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ in select_input()
1896 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ in select_input()
1897 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ in select_input()
1898 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ in select_input()
1899 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, in select_input()
1901 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ in select_input()
1902 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ in select_input()
1903 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ in select_input()
1904 hdmi_write(sd, 0x89, 0x04); /* equaliser */ in select_input()
1905 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ in select_input()
1906 hdmi_write(sd, 0x93, 0x04); /* equaliser */ in select_input()
1907 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ in select_input()
1908 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ in select_input()
1909 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ in select_input()
1910 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ in select_input()
1912 afe_write(sd, 0x00, 0xff); /* power down ADC */ in select_input()
1913 afe_write(sd, 0xc8, 0x40); /* phase control */ in select_input()
1916 cp_write(sd, 0x73, 0x10); in select_input()
1917 cp_write(sd, 0x74, 0x04); in select_input()
1918 cp_write(sd, 0x75, 0x01); in select_input()
1919 cp_write(sd, 0x76, 0x00); in select_input()
1924 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ in select_input()
1925 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ in select_input()
1926 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ in select_input()
1929 cp_write(sd, 0xc3, 0x33); /* Component mode */ in select_input()
1932 io_write_and_or(sd, 0x02, 0x0f, 0xf0); in select_input()
1936 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", in select_input()
1942 static int adv7842_s_routing(struct v4l2_subdev *sd, in adv7842_s_routing() argument
1945 struct adv7842_state *state = to_state(sd); in adv7842_s_routing()
1947 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); in adv7842_s_routing()
1980 disable_input(sd); in adv7842_s_routing()
1981 select_input(sd, state->vid_std_select); in adv7842_s_routing()
1982 enable_input(sd); in adv7842_s_routing()
1984 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); in adv7842_s_routing()
1989 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd, in adv7842_enum_mbus_code() argument
2053 struct v4l2_subdev *sd = &state->sd; in adv7842_setup_format() local
2055 io_write_clr_set(sd, 0x02, 0x02, in adv7842_setup_format()
2057 io_write(sd, 0x03, state->format->op_format_sel | in adv7842_setup_format()
2059 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state)); in adv7842_setup_format()
2060 io_write_clr_set(sd, 0x05, 0x01, in adv7842_setup_format()
2064 static int adv7842_get_format(struct v4l2_subdev *sd, in adv7842_get_format() argument
2068 struct adv7842_state *state = to_state(sd); in adv7842_get_format()
2075 if (!(sdp_read(sd, 0x5a) & 0x01)) in adv7842_get_format()
2093 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv7842_get_format()
2102 static int adv7842_set_format(struct v4l2_subdev *sd, in adv7842_set_format() argument
2106 struct adv7842_state *state = to_state(sd); in adv7842_set_format()
2113 return adv7842_get_format(sd, cfg, format); in adv7842_set_format()
2125 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv7842_set_format()
2135 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) in adv7842_irq_enable() argument
2139 io_write(sd, 0x46, 0x9c); in adv7842_irq_enable()
2141 io_write(sd, 0x5a, 0x10); in adv7842_irq_enable()
2143 io_write(sd, 0x73, 0x03); in adv7842_irq_enable()
2145 io_write(sd, 0x78, 0x03); in adv7842_irq_enable()
2147 io_write(sd, 0xa0, 0x09); in adv7842_irq_enable()
2149 io_write(sd, 0x69, 0x08); in adv7842_irq_enable()
2151 io_write(sd, 0x46, 0x0); in adv7842_irq_enable()
2152 io_write(sd, 0x5a, 0x0); in adv7842_irq_enable()
2153 io_write(sd, 0x73, 0x0); in adv7842_irq_enable()
2154 io_write(sd, 0x78, 0x0); in adv7842_irq_enable()
2155 io_write(sd, 0xa0, 0x0); in adv7842_irq_enable()
2156 io_write(sd, 0x69, 0x0); in adv7842_irq_enable()
2160 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) in adv7842_isr() argument
2162 struct adv7842_state *state = to_state(sd); in adv7842_isr()
2166 adv7842_irq_enable(sd, false); in adv7842_isr()
2169 irq_status[0] = io_read(sd, 0x43); in adv7842_isr()
2170 irq_status[1] = io_read(sd, 0x57); in adv7842_isr()
2171 irq_status[2] = io_read(sd, 0x70); in adv7842_isr()
2172 irq_status[3] = io_read(sd, 0x75); in adv7842_isr()
2173 irq_status[4] = io_read(sd, 0x9d); in adv7842_isr()
2174 irq_status[5] = io_read(sd, 0x66); in adv7842_isr()
2178 io_write(sd, 0x44, irq_status[0]); in adv7842_isr()
2180 io_write(sd, 0x58, irq_status[1]); in adv7842_isr()
2182 io_write(sd, 0x71, irq_status[2]); in adv7842_isr()
2184 io_write(sd, 0x76, irq_status[3]); in adv7842_isr()
2186 io_write(sd, 0x9e, irq_status[4]); in adv7842_isr()
2188 io_write(sd, 0x67, irq_status[5]); in adv7842_isr()
2190 adv7842_irq_enable(sd, true); in adv7842_isr()
2192 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, in adv7842_isr()
2206 if (is_digital_input(sd)) in adv7842_isr()
2213 v4l2_dbg(1, debug, sd, in adv7842_isr()
2217 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); in adv7842_isr()
2224 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, in adv7842_isr()
2225 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); in adv7842_isr()
2226 set_rgb_quantization_range(sd); in adv7842_isr()
2233 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); in adv7842_isr()
2234 adv7842_s_detect_tx_5v_ctrl(sd); in adv7842_isr()
2241 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) in adv7842_get_edid() argument
2243 struct adv7842_state *state = to_state(sd); in adv7842_get_edid()
2281 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) in adv7842_set_edid() argument
2283 struct adv7842_state *state = to_state(sd); in adv7842_set_edid()
2306 err = edid_write_vga_segment(sd); in adv7842_set_edid()
2316 err = edid_write_hdmi_segment(sd, e->pad); in adv7842_set_edid()
2322 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); in adv7842_set_edid()
2333 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri) in log_infoframe() argument
2339 struct i2c_client *client = v4l2_get_subdevdata(sd); in log_infoframe()
2342 if (!(io_read(sd, 0x60) & cri->present_mask)) { in log_infoframe()
2343 v4l2_info(sd, "%s infoframe not received\n", cri->desc); in log_infoframe()
2348 buffer[i] = infoframe_read(sd, cri->head_addr + i); in log_infoframe()
2353 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); in log_infoframe()
2358 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); in log_infoframe()
2361 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); in log_infoframe()
2368 static void adv7842_log_infoframes(struct v4l2_subdev *sd) in adv7842_log_infoframes() argument
2378 if (!(hdmi_read(sd, 0x05) & 0x80)) { in adv7842_log_infoframes()
2379 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); in adv7842_log_infoframes()
2384 log_infoframe(sd, &cri[i]); in adv7842_log_infoframes()
2406 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) in adv7842_sdp_log_status() argument
2409 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; in adv7842_sdp_log_status()
2411 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); in adv7842_sdp_log_status()
2412 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", in adv7842_sdp_log_status()
2413 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); in adv7842_sdp_log_status()
2415 v4l2_info(sd, "SDP: free run: %s\n", in adv7842_sdp_log_status()
2416 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); in adv7842_sdp_log_status()
2417 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? in adv7842_sdp_log_status()
2434 v4l2_info(sd, "SDP: standard %s\n", in adv7842_sdp_log_status()
2435 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); in adv7842_sdp_log_status()
2436 v4l2_info(sd, "SDP: %s\n", in adv7842_sdp_log_status()
2437 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); in adv7842_sdp_log_status()
2438 v4l2_info(sd, "SDP: %s\n", in adv7842_sdp_log_status()
2439 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); in adv7842_sdp_log_status()
2440 v4l2_info(sd, "SDP: deinterlacer %s\n", in adv7842_sdp_log_status()
2441 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); in adv7842_sdp_log_status()
2442 v4l2_info(sd, "SDP: csc %s mode\n", in adv7842_sdp_log_status()
2443 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); in adv7842_sdp_log_status()
2448 static int adv7842_cp_log_status(struct v4l2_subdev *sd) in adv7842_cp_log_status() argument
2451 struct adv7842_state *state = to_state(sd); in adv7842_cp_log_status()
2453 u8 reg_io_0x02 = io_read(sd, 0x02); in adv7842_cp_log_status()
2454 u8 reg_io_0x21 = io_read(sd, 0x21); in adv7842_cp_log_status()
2455 u8 reg_rep_0x77 = rep_read(sd, 0x77); in adv7842_cp_log_status()
2456 u8 reg_rep_0x7d = rep_read(sd, 0x7d); in adv7842_cp_log_status()
2457 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; in adv7842_cp_log_status()
2458 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; in adv7842_cp_log_status()
2459 bool audio_mute = io_read(sd, 0x65) & 0x40; in adv7842_cp_log_status()
2487 v4l2_info(sd, "-----Chip status-----\n"); in adv7842_cp_log_status()
2488 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); in adv7842_cp_log_status()
2489 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", in adv7842_cp_log_status()
2491 v4l2_info(sd, "EDID A %s, B %s\n", in adv7842_cp_log_status()
2496 v4l2_info(sd, "HPD A %s, B %s\n", in adv7842_cp_log_status()
2499 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? in adv7842_cp_log_status()
2502 v4l2_info(sd, "-----Signal status-----\n"); in adv7842_cp_log_status()
2504 v4l2_info(sd, "Cable detected (+5V power): %s\n", in adv7842_cp_log_status()
2505 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); in adv7842_cp_log_status()
2506 v4l2_info(sd, "TMDS signal detected: %s\n", in adv7842_cp_log_status()
2507 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); in adv7842_cp_log_status()
2508 v4l2_info(sd, "TMDS signal locked: %s\n", in adv7842_cp_log_status()
2509 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); in adv7842_cp_log_status()
2511 v4l2_info(sd, "Cable detected (+5V power):%s\n", in adv7842_cp_log_status()
2512 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); in adv7842_cp_log_status()
2513 v4l2_info(sd, "TMDS signal detected: %s\n", in adv7842_cp_log_status()
2514 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); in adv7842_cp_log_status()
2515 v4l2_info(sd, "TMDS signal locked: %s\n", in adv7842_cp_log_status()
2516 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); in adv7842_cp_log_status()
2518 v4l2_info(sd, "CP free run: %s\n", in adv7842_cp_log_status()
2519 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); in adv7842_cp_log_status()
2520 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", in adv7842_cp_log_status()
2521 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, in adv7842_cp_log_status()
2522 (io_read(sd, 0x01) & 0x70) >> 4); in adv7842_cp_log_status()
2524 v4l2_info(sd, "-----Video Timings-----\n"); in adv7842_cp_log_status()
2525 if (no_cp_signal(sd)) { in adv7842_cp_log_status()
2526 v4l2_info(sd, "STDI: not locked\n"); in adv7842_cp_log_status()
2528 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); in adv7842_cp_log_status()
2529 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); in adv7842_cp_log_status()
2530 u32 lcvs = cp_read(sd, 0xb3) >> 3; in adv7842_cp_log_status()
2531 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); in adv7842_cp_log_status()
2532 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? in adv7842_cp_log_status()
2533 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2534 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? in adv7842_cp_log_status()
2535 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2536 v4l2_info(sd, in adv7842_cp_log_status()
2539 (cp_read(sd, 0xb1) & 0x40) ? in adv7842_cp_log_status()
2543 if (adv7842_query_dv_timings(sd, &timings)) in adv7842_cp_log_status()
2544 v4l2_info(sd, "No video detected\n"); in adv7842_cp_log_status()
2546 v4l2_print_dv_timings(sd->name, "Detected format: ", in adv7842_cp_log_status()
2548 v4l2_print_dv_timings(sd->name, "Configured format: ", in adv7842_cp_log_status()
2551 if (no_cp_signal(sd)) in adv7842_cp_log_status()
2554 v4l2_info(sd, "-----Color space-----\n"); in adv7842_cp_log_status()
2555 v4l2_info(sd, "RGB quantization range ctrl: %s\n", in adv7842_cp_log_status()
2557 v4l2_info(sd, "Input color space: %s\n", in adv7842_cp_log_status()
2559 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", in adv7842_cp_log_status()
2564 v4l2_info(sd, "Color space conversion: %s\n", in adv7842_cp_log_status()
2565 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); in adv7842_cp_log_status()
2567 if (!is_digital_input(sd)) in adv7842_cp_log_status()
2570 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); in adv7842_cp_log_status()
2571 v4l2_info(sd, "HDCP encrypted content: %s\n", in adv7842_cp_log_status()
2572 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); in adv7842_cp_log_status()
2573 v4l2_info(sd, "HDCP keys read: %s%s\n", in adv7842_cp_log_status()
2574 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", in adv7842_cp_log_status()
2575 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); in adv7842_cp_log_status()
2576 if (!is_hdmi(sd)) in adv7842_cp_log_status()
2579 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", in adv7842_cp_log_status()
2584 v4l2_info(sd, "Audio format: %s\n", in adv7842_cp_log_status()
2585 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); in adv7842_cp_log_status()
2587 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + in adv7842_cp_log_status()
2588 (hdmi_read(sd, 0x5c) << 8) + in adv7842_cp_log_status()
2589 (hdmi_read(sd, 0x5d) & 0xf0)); in adv7842_cp_log_status()
2590 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + in adv7842_cp_log_status()
2591 (hdmi_read(sd, 0x5e) << 8) + in adv7842_cp_log_status()
2592 hdmi_read(sd, 0x5f)); in adv7842_cp_log_status()
2593 v4l2_info(sd, "AV Mute: %s\n", in adv7842_cp_log_status()
2594 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); in adv7842_cp_log_status()
2595 v4l2_info(sd, "Deep color mode: %s\n", in adv7842_cp_log_status()
2596 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); in adv7842_cp_log_status()
2598 adv7842_log_infoframes(sd); in adv7842_cp_log_status()
2603 static int adv7842_log_status(struct v4l2_subdev *sd) in adv7842_log_status() argument
2605 struct adv7842_state *state = to_state(sd); in adv7842_log_status()
2608 return adv7842_sdp_log_status(sd); in adv7842_log_status()
2609 return adv7842_cp_log_status(sd); in adv7842_log_status()
2612 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) in adv7842_querystd() argument
2614 struct adv7842_state *state = to_state(sd); in adv7842_querystd()
2616 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_querystd()
2621 if (!(sdp_read(sd, 0x5A) & 0x01)) { in adv7842_querystd()
2623 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); in adv7842_querystd()
2627 switch (sdp_read(sd, 0x52) & 0x0f) { in adv7842_querystd()
2667 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) in adv7842_s_sdp_io() argument
2670 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2671 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); in adv7842_s_sdp_io()
2672 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); in adv7842_s_sdp_io()
2673 sdp_io_write(sd, 0x97, s->hs_width & 0xff); in adv7842_s_sdp_io()
2674 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2675 sdp_io_write(sd, 0x99, s->de_beg & 0xff); in adv7842_s_sdp_io()
2676 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); in adv7842_s_sdp_io()
2677 sdp_io_write(sd, 0x9b, s->de_end & 0xff); in adv7842_s_sdp_io()
2678 sdp_io_write(sd, 0xa8, s->vs_beg_o); in adv7842_s_sdp_io()
2679 sdp_io_write(sd, 0xa9, s->vs_beg_e); in adv7842_s_sdp_io()
2680 sdp_io_write(sd, 0xaa, s->vs_end_o); in adv7842_s_sdp_io()
2681 sdp_io_write(sd, 0xab, s->vs_end_e); in adv7842_s_sdp_io()
2682 sdp_io_write(sd, 0xac, s->de_v_beg_o); in adv7842_s_sdp_io()
2683 sdp_io_write(sd, 0xad, s->de_v_beg_e); in adv7842_s_sdp_io()
2684 sdp_io_write(sd, 0xae, s->de_v_end_o); in adv7842_s_sdp_io()
2685 sdp_io_write(sd, 0xaf, s->de_v_end_e); in adv7842_s_sdp_io()
2688 sdp_io_write(sd, 0x94, 0x00); in adv7842_s_sdp_io()
2689 sdp_io_write(sd, 0x95, 0x00); in adv7842_s_sdp_io()
2690 sdp_io_write(sd, 0x96, 0x00); in adv7842_s_sdp_io()
2691 sdp_io_write(sd, 0x97, 0x20); in adv7842_s_sdp_io()
2692 sdp_io_write(sd, 0x98, 0x00); in adv7842_s_sdp_io()
2693 sdp_io_write(sd, 0x99, 0x00); in adv7842_s_sdp_io()
2694 sdp_io_write(sd, 0x9a, 0x00); in adv7842_s_sdp_io()
2695 sdp_io_write(sd, 0x9b, 0x00); in adv7842_s_sdp_io()
2696 sdp_io_write(sd, 0xa8, 0x04); in adv7842_s_sdp_io()
2697 sdp_io_write(sd, 0xa9, 0x04); in adv7842_s_sdp_io()
2698 sdp_io_write(sd, 0xaa, 0x04); in adv7842_s_sdp_io()
2699 sdp_io_write(sd, 0xab, 0x04); in adv7842_s_sdp_io()
2700 sdp_io_write(sd, 0xac, 0x04); in adv7842_s_sdp_io()
2701 sdp_io_write(sd, 0xad, 0x04); in adv7842_s_sdp_io()
2702 sdp_io_write(sd, 0xae, 0x04); in adv7842_s_sdp_io()
2703 sdp_io_write(sd, 0xaf, 0x04); in adv7842_s_sdp_io()
2707 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) in adv7842_s_std() argument
2709 struct adv7842_state *state = to_state(sd); in adv7842_s_std()
2712 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_s_std()
2718 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); in adv7842_s_std()
2720 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); in adv7842_s_std()
2722 adv7842_s_sdp_io(sd, NULL); in adv7842_s_std()
2731 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) in adv7842_g_std() argument
2733 struct adv7842_state *state = to_state(sd); in adv7842_g_std()
2735 v4l2_dbg(1, debug, sd, "%s:\n", __func__); in adv7842_g_std()
2746 static int adv7842_core_init(struct v4l2_subdev *sd) in adv7842_core_init() argument
2748 struct adv7842_state *state = to_state(sd); in adv7842_core_init()
2750 hdmi_write(sd, 0x48, in adv7842_core_init()
2754 disable_input(sd); in adv7842_core_init()
2760 rep_write_and_or(sd, 0x77, 0xd3, 0x20); in adv7842_core_init()
2763 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ in adv7842_core_init()
2764 io_write(sd, 0x15, 0x80); /* Power up pads */ in adv7842_core_init()
2767 io_write(sd, 0x02, in adv7842_core_init()
2772 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | in adv7842_core_init()
2778 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ in adv7842_core_init()
2781 io_write_and_or(sd, 0x14, 0xc0, in adv7842_core_init()
2787 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | in adv7842_core_init()
2791 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | in adv7842_core_init()
2797 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ in adv7842_core_init()
2798 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ in adv7842_core_init()
2799 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ in adv7842_core_init()
2800 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ in adv7842_core_init()
2802 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ in adv7842_core_init()
2803 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); in adv7842_core_init()
2805 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); in adv7842_core_init()
2809 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ in adv7842_core_init()
2812 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ in adv7842_core_init()
2813 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ in adv7842_core_init()
2814 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
2815 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
2816 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
2818 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ in adv7842_core_init()
2819 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ in adv7842_core_init()
2820 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, in adv7842_core_init()
2822 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ in adv7842_core_init()
2823 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
2824 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
2825 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
2832 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ in adv7842_core_init()
2835 select_input(sd, pdata->vid_std_select); in adv7842_core_init()
2837 enable_input(sd); in adv7842_core_init()
2841 hdmi_write(sd, 0x69, 0x5c); in adv7842_core_init()
2844 hdmi_write(sd, 0x69, 0xa3); in adv7842_core_init()
2846 io_write_and_or(sd, 0x20, 0xcf, 0x00); in adv7842_core_init()
2850 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); in adv7842_core_init()
2851 io_write(sd, 0x33, 0x40); in adv7842_core_init()
2854 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ in adv7842_core_init()
2856 adv7842_irq_enable(sd, true); in adv7842_core_init()
2858 return v4l2_ctrl_handler_setup(sd->ctrl_handler); in adv7842_core_init()
2863 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) in adv7842_ddr_ram_test() argument
2876 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ in adv7842_ddr_ram_test()
2877 io_write(sd, 0x01, 0x00); /* Program SDP mode */ in adv7842_ddr_ram_test()
2878 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ in adv7842_ddr_ram_test()
2879 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2880 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2881 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2882 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ in adv7842_ddr_ram_test()
2883 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2884 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ in adv7842_ddr_ram_test()
2885 io_write(sd, 0x15, 0xBA); /* Enable outputs */ in adv7842_ddr_ram_test()
2886 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ in adv7842_ddr_ram_test()
2887 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ in adv7842_ddr_ram_test()
2891 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ in adv7842_ddr_ram_test()
2892 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2893 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2894 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2895 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2896 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2897 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2898 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2899 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2900 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2901 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
2905 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ in adv7842_ddr_ram_test()
2906 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ in adv7842_ddr_ram_test()
2911 u8 result = sdp_io_read(sd, 0xdb); in adv7842_ddr_ram_test()
2922 v4l2_dbg(1, debug, sd, in adv7842_ddr_ram_test()
2931 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, in adv7842_rewrite_i2c_addresses() argument
2934 io_write(sd, 0xf1, pdata->i2c_sdp << 1); in adv7842_rewrite_i2c_addresses()
2935 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); in adv7842_rewrite_i2c_addresses()
2936 io_write(sd, 0xf3, pdata->i2c_avlink << 1); in adv7842_rewrite_i2c_addresses()
2937 io_write(sd, 0xf4, pdata->i2c_cec << 1); in adv7842_rewrite_i2c_addresses()
2938 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); in adv7842_rewrite_i2c_addresses()
2940 io_write(sd, 0xf8, pdata->i2c_afe << 1); in adv7842_rewrite_i2c_addresses()
2941 io_write(sd, 0xf9, pdata->i2c_repeater << 1); in adv7842_rewrite_i2c_addresses()
2942 io_write(sd, 0xfa, pdata->i2c_edid << 1); in adv7842_rewrite_i2c_addresses()
2943 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); in adv7842_rewrite_i2c_addresses()
2945 io_write(sd, 0xfd, pdata->i2c_cp << 1); in adv7842_rewrite_i2c_addresses()
2946 io_write(sd, 0xfe, pdata->i2c_vdp << 1); in adv7842_rewrite_i2c_addresses()
2949 static int adv7842_command_ram_test(struct v4l2_subdev *sd) in adv7842_command_ram_test() argument
2951 struct i2c_client *client = v4l2_get_subdevdata(sd); in adv7842_command_ram_test()
2952 struct adv7842_state *state = to_state(sd); in adv7842_command_ram_test()
2961 v4l2_info(sd, "no sdram or no ddr sdram\n"); in adv7842_command_ram_test()
2965 main_reset(sd); in adv7842_command_ram_test()
2967 adv7842_rewrite_i2c_addresses(sd, pdata); in adv7842_command_ram_test()
2970 ret = adv7842_ddr_ram_test(sd); in adv7842_command_ram_test()
2972 main_reset(sd); in adv7842_command_ram_test()
2974 adv7842_rewrite_i2c_addresses(sd, pdata); in adv7842_command_ram_test()
2977 adv7842_core_init(sd); in adv7842_command_ram_test()
2979 disable_input(sd); in adv7842_command_ram_test()
2981 select_input(sd, state->vid_std_select); in adv7842_command_ram_test()
2983 enable_input(sd); in adv7842_command_ram_test()
2985 edid_write_vga_segment(sd); in adv7842_command_ram_test()
2986 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); in adv7842_command_ram_test()
2987 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); in adv7842_command_ram_test()
2993 adv7842_s_dv_timings(sd, &timings); in adv7842_command_ram_test()
2998 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) in adv7842_ioctl() argument
3002 return adv7842_command_ram_test(sd); in adv7842_ioctl()
3007 static int adv7842_subscribe_event(struct v4l2_subdev *sd, in adv7842_subscribe_event() argument
3013 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); in adv7842_subscribe_event()
3015 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); in adv7842_subscribe_event()
3099 static void adv7842_unregister_clients(struct v4l2_subdev *sd) in adv7842_unregister_clients() argument
3101 struct adv7842_state *state = to_state(sd); in adv7842_unregister_clients()
3138 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, in adv7842_dummy_client() argument
3141 struct i2c_client *client = v4l2_get_subdevdata(sd); in adv7842_dummy_client()
3144 io_write(sd, io_reg, addr << 1); in adv7842_dummy_client()
3147 v4l2_err(sd, "no %s i2c addr configured\n", desc); in adv7842_dummy_client()
3151 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); in adv7842_dummy_client()
3153 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr); in adv7842_dummy_client()
3158 static int adv7842_register_clients(struct v4l2_subdev *sd) in adv7842_register_clients() argument
3160 struct adv7842_state *state = to_state(sd); in adv7842_register_clients()
3163 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); in adv7842_register_clients()
3164 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); in adv7842_register_clients()
3165 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); in adv7842_register_clients()
3166 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); in adv7842_register_clients()
3167 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); in adv7842_register_clients()
3168 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); in adv7842_register_clients()
3169 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); in adv7842_register_clients()
3170 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); in adv7842_register_clients()
3171 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); in adv7842_register_clients()
3172 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); in adv7842_register_clients()
3173 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); in adv7842_register_clients()
3199 struct v4l2_subdev *sd; in adv7842_probe() local
3226 sd = &state->sd; in adv7842_probe()
3227 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); in adv7842_probe()
3228 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; in adv7842_probe()
3238 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); in adv7842_probe()
3243 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", in adv7842_probe()
3249 main_reset(sd); in adv7842_probe()
3278 sd->ctrl_handler = hdl; in adv7842_probe()
3289 if (adv7842_s_detect_tx_5v_ctrl(sd)) { in adv7842_probe()
3294 if (adv7842_register_clients(sd) < 0) { in adv7842_probe()
3296 v4l2_err(sd, "failed to create all i2c clients\n"); in adv7842_probe()
3303 v4l2_err(sd, "Could not create work queue\n"); in adv7842_probe()
3312 err = media_entity_init(&sd->entity, 1, &state->pad, 0); in adv7842_probe()
3316 err = adv7842_core_init(sd); in adv7842_probe()
3320 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, in adv7842_probe()
3325 media_entity_cleanup(&sd->entity); in adv7842_probe()
3330 adv7842_unregister_clients(sd); in adv7842_probe()
3340 struct v4l2_subdev *sd = i2c_get_clientdata(client); in adv7842_remove() local
3341 struct adv7842_state *state = to_state(sd); in adv7842_remove()
3343 adv7842_irq_enable(sd, false); in adv7842_remove()
3347 v4l2_device_unregister_subdev(sd); in adv7842_remove()
3348 media_entity_cleanup(&sd->entity); in adv7842_remove()
3349 adv7842_unregister_clients(sd); in adv7842_remove()
3350 v4l2_ctrl_handler_free(sd->ctrl_handler); in adv7842_remove()