Lines Matching refs:timings
176 struct v4l2_dv_timings timings; member
276 struct v4l2_dv_timings timings; member
902 const struct v4l2_dv_timings *timings) in find_and_set_predefined_video_timings() argument
906 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { in find_and_set_predefined_video_timings()
907 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, in find_and_set_predefined_video_timings()
920 struct v4l2_dv_timings *timings) in configure_predefined_video_timings() argument
947 0x01, adv7604_prim_mode_comp, timings); in configure_predefined_video_timings()
950 0x02, adv7604_prim_mode_gr, timings); in configure_predefined_video_timings()
953 0x05, adv76xx_prim_mode_hdmi_comp, timings); in configure_predefined_video_timings()
956 0x06, adv76xx_prim_mode_hdmi_gr, timings); in configure_predefined_video_timings()
1122 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { in set_rgb_quantization_range()
1326 struct v4l2_dv_timings *timings) in stdi2dv_timings() argument
1343 *timings = adv76xx_timings[i]; in stdi2dv_timings()
1351 false, timings)) in stdi2dv_timings()
1356 false, state->aspect_ratio, timings)) in stdi2dv_timings()
1424 struct v4l2_enum_dv_timings *timings) in adv76xx_enum_dv_timings() argument
1428 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1) in adv76xx_enum_dv_timings()
1431 if (timings->pad >= state->source_pad) in adv76xx_enum_dv_timings()
1434 memset(timings->reserved, 0, sizeof(timings->reserved)); in adv76xx_enum_dv_timings()
1435 timings->timings = adv76xx_timings[timings->index]; in adv76xx_enum_dv_timings()
1476 struct v4l2_dv_timings *timings) in adv76xx_fill_optional_dv_timings_fields() argument
1481 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i], in adv76xx_fill_optional_dv_timings_fields()
1483 *timings = adv76xx_timings[i]; in adv76xx_fill_optional_dv_timings_fields()
1522 struct v4l2_dv_timings *timings) in adv76xx_query_dv_timings() argument
1526 struct v4l2_bt_timings *bt = &timings->bt; in adv76xx_query_dv_timings()
1529 if (!timings) in adv76xx_query_dv_timings()
1532 memset(timings, 0, sizeof(struct v4l2_dv_timings)); in adv76xx_query_dv_timings()
1549 timings->type = V4L2_DV_BT_656_1120; in adv76xx_query_dv_timings()
1574 adv76xx_fill_optional_dv_timings_fields(sd, timings); in adv76xx_query_dv_timings()
1580 if (!stdi2dv_timings(sd, &stdi, timings)) in adv76xx_query_dv_timings()
1584 if (!stdi2dv_timings(sd, &stdi, timings)) in adv76xx_query_dv_timings()
1588 if (stdi2dv_timings(sd, &stdi, timings)) { in adv76xx_query_dv_timings()
1619 memset(timings, 0, sizeof(struct v4l2_dv_timings)); in adv76xx_query_dv_timings()
1632 timings, true); in adv76xx_query_dv_timings()
1638 struct v4l2_dv_timings *timings) in adv76xx_s_dv_timings() argument
1644 if (!timings) in adv76xx_s_dv_timings()
1647 if (v4l2_match_dv_timings(&state->timings, timings, 0)) { in adv76xx_s_dv_timings()
1652 bt = &timings->bt; in adv76xx_s_dv_timings()
1661 adv76xx_fill_optional_dv_timings_fields(sd, timings); in adv76xx_s_dv_timings()
1663 state->timings = *timings; in adv76xx_s_dv_timings()
1668 err = configure_predefined_video_timings(sd, timings); in adv76xx_s_dv_timings()
1679 timings, true); in adv76xx_s_dv_timings()
1684 struct v4l2_dv_timings *timings) in adv76xx_g_dv_timings() argument
1688 *timings = state->timings; in adv76xx_g_dv_timings()
1804 format->width = state->timings.bt.width; in adv76xx_fill_format()
1805 format->height = state->timings.bt.height; in adv76xx_fill_format()
1809 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) in adv76xx_fill_format()
1810 format->colorspace = (state->timings.bt.height <= 576) ? in adv76xx_fill_format()
2220 struct v4l2_dv_timings timings; in adv76xx_log_status() local
2299 if (adv76xx_query_dv_timings(sd, &timings)) in adv76xx_log_status()
2303 &timings, true); in adv76xx_log_status()
2305 &state->timings, true); in adv76xx_log_status()
3068 state->timings = cea640x480; in adv76xx_probe()