906 	for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {  in find_and_set_predefined_video_timings()
968 		const struct v4l2_bt_timings *bt)  in configure_custom_video_timings()  argument
971 	u32 width = htotal(bt);  in configure_custom_video_timings()
972 	u32 height = vtotal(bt);  in configure_custom_video_timings()
973 	u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;  in configure_custom_video_timings()
974 	u16 cp_start_eav = width - bt->hfrontporch;  in configure_custom_video_timings()
975 	u16 cp_start_vbi = height - bt->vfrontporch;  in configure_custom_video_timings()
976 	u16 cp_end_vbi = bt->vsync + bt->vbackporch;  in configure_custom_video_timings()
977 	u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?  in configure_custom_video_timings()
978 		((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;  in configure_custom_video_timings()
1122 		if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {  in set_rgb_quantization_range()
1333 	for (i = 0; adv76xx_timings[i].bt.height; i++) {  in stdi2dv_timings()
1334 		if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)  in stdi2dv_timings()
1336 		if (adv76xx_timings[i].bt.vsync != stdi->lcvs)  in stdi2dv_timings()
1339 		pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);  in stdi2dv_timings()
1341 		if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&  in stdi2dv_timings()
1342 		    (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {  in stdi2dv_timings()
1448 	cap->bt.max_width = 1920;  in adv76xx_dv_timings_cap()
1449 	cap->bt.max_height = 1200;  in adv76xx_dv_timings_cap()
1450 	cap->bt.min_pixelclock = 25000000;  in adv76xx_dv_timings_cap()
1457 		cap->bt.max_pixelclock = 225000000;  in adv76xx_dv_timings_cap()
1462 		cap->bt.max_pixelclock = 170000000;  in adv76xx_dv_timings_cap()
1466 	cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |  in adv76xx_dv_timings_cap()
1468 	cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |  in adv76xx_dv_timings_cap()
1480 	for (i = 0; adv76xx_timings[i].bt.width; i++) {  in adv76xx_fill_optional_dv_timings_fields()
1526 	struct v4l2_bt_timings *bt = &timings->bt;  in adv76xx_query_dv_timings()  local
1545 	bt->interlaced = stdi.interlaced ?  in adv76xx_query_dv_timings()
1551 		bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);  in adv76xx_query_dv_timings()
1552 		bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);  in adv76xx_query_dv_timings()
1553 		bt->pixelclock = info->read_hdmi_pixelclock(sd);  in adv76xx_query_dv_timings()
1554 		bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);  in adv76xx_query_dv_timings()
1555 		bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);  in adv76xx_query_dv_timings()
1556 		bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);  in adv76xx_query_dv_timings()
1557 		bt->vfrontporch = hdmi_read16(sd, 0x2a,  in adv76xx_query_dv_timings()
1559 		bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;  in adv76xx_query_dv_timings()
1560 		bt->vbackporch = hdmi_read16(sd, 0x32,  in adv76xx_query_dv_timings()
1562 		bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |  in adv76xx_query_dv_timings()
1564 		if (bt->interlaced == V4L2_DV_INTERLACED) {  in adv76xx_query_dv_timings()
1565 			bt->height += hdmi_read16(sd, 0x0b,  in adv76xx_query_dv_timings()
1567 			bt->il_vfrontporch = hdmi_read16(sd, 0x2c,  in adv76xx_query_dv_timings()
1569 			bt->il_vsync = hdmi_read16(sd, 0x30,  in adv76xx_query_dv_timings()
1571 			bt->il_vbackporch = hdmi_read16(sd, 0x34,  in adv76xx_query_dv_timings()
1623 	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||  in adv76xx_query_dv_timings()
1624 			(is_digital_input(sd) && bt->pixelclock > 225000000)) {  in adv76xx_query_dv_timings()
1626 				__func__, (u32)bt->pixelclock);  in adv76xx_query_dv_timings()
1641 	struct v4l2_bt_timings *bt;  in adv76xx_s_dv_timings()  local
1652 	bt = &timings->bt;  in adv76xx_s_dv_timings()
1654 	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||  in adv76xx_s_dv_timings()
1655 			(is_digital_input(sd) && bt->pixelclock > 225000000)) {  in adv76xx_s_dv_timings()
1657 				__func__, (u32)bt->pixelclock);  in adv76xx_s_dv_timings()
1665 	cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);  in adv76xx_s_dv_timings()
1672 		configure_custom_video_timings(sd, bt);  in adv76xx_s_dv_timings()
1804 	format->width = state->timings.bt.width;  in adv76xx_fill_format()
1805 	format->height = state->timings.bt.height;  in adv76xx_fill_format()
1809 	if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)  in adv76xx_fill_format()
1810 		format->colorspace = (state->timings.bt.height <= 576) ?  in adv76xx_fill_format()