59 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)  in ves1820_writereg()  argument
62 	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };  in ves1820_writereg()
65 	ret = i2c_transfer(state->i2c, &msg, 1);  in ves1820_writereg()
74 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)  in ves1820_readreg()  argument
79 		{.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},  in ves1820_readreg()
80 		{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}  in ves1820_readreg()
84 	ret = i2c_transfer(state->i2c, msg, 2);  in ves1820_readreg()
93 static int ves1820_setup_reg0(struct ves1820_state *state,  in ves1820_setup_reg0()  argument
96 	reg0 |= state->reg0 & 0x62;  in ves1820_setup_reg0()
99 		if (!state->config->invert) reg0 |= 0x20;  in ves1820_setup_reg0()
102 		if (!state->config->invert) reg0 &= ~0x20;  in ves1820_setup_reg0()
106 	ves1820_writereg(state, 0x00, reg0 & 0xfe);  in ves1820_setup_reg0()
107 	ves1820_writereg(state, 0x00, reg0 | 0x01);  in ves1820_setup_reg0()
109 	state->reg0 = reg0;  in ves1820_setup_reg0()
114 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)  in ves1820_set_symbolrate()  argument
126 	if (symbolrate > state->config->xin / 2)  in ves1820_set_symbolrate()
127 		symbolrate = state->config->xin / 2;  in ves1820_set_symbolrate()
132 	if (symbolrate < state->config->xin / 16)  in ves1820_set_symbolrate()
134 	if (symbolrate < state->config->xin / 32)  in ves1820_set_symbolrate()
136 	if (symbolrate < state->config->xin / 64)  in ves1820_set_symbolrate()
140 	fpxin = state->config->xin * 10;  in ves1820_set_symbolrate()
163 	fin = state->config->xin >> 4;  in ves1820_set_symbolrate()
172 	BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;  in ves1820_set_symbolrate()
181 	ves1820_writereg(state, 0x03, NDEC);  in ves1820_set_symbolrate()
182 	ves1820_writereg(state, 0x0a, BDR & 0xff);  in ves1820_set_symbolrate()
183 	ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);  in ves1820_set_symbolrate()
184 	ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);  in ves1820_set_symbolrate()
186 	ves1820_writereg(state, 0x0d, BDRI);  in ves1820_set_symbolrate()
187 	ves1820_writereg(state, 0x0e, SFIL);  in ves1820_set_symbolrate()
194 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_init()  local
197 	ves1820_writereg(state, 0, 0);  in ves1820_init()
200 		ves1820_writereg(state, i, ves1820_inittab[i]);  in ves1820_init()
201 	if (state->config->selagc)  in ves1820_init()
202 		ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);  in ves1820_init()
204 	ves1820_writereg(state, 0x34, state->pwm);  in ves1820_init()
212 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_set_parameters()  local
228 	ves1820_set_symbolrate(state, p->symbol_rate);  in ves1820_set_parameters()
229 	ves1820_writereg(state, 0x34, state->pwm);  in ves1820_set_parameters()
231 	ves1820_writereg(state, 0x01, reg0x01[real_qam]);  in ves1820_set_parameters()
232 	ves1820_writereg(state, 0x05, reg0x05[real_qam]);  in ves1820_set_parameters()
233 	ves1820_writereg(state, 0x08, reg0x08[real_qam]);  in ves1820_set_parameters()
234 	ves1820_writereg(state, 0x09, reg0x09[real_qam]);  in ves1820_set_parameters()
236 	ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);  in ves1820_set_parameters()
237 	ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));  in ves1820_set_parameters()
244 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_read_status()  local
248 	sync = ves1820_readreg(state, 0x11);  in ves1820_read_status()
270 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_read_ber()  local
272 	u32 _ber = ves1820_readreg(state, 0x14) |  in ves1820_read_ber()
273 			(ves1820_readreg(state, 0x15) << 8) |  in ves1820_read_ber()
274 			((ves1820_readreg(state, 0x16) & 0x0f) << 16);  in ves1820_read_ber()
282 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_read_signal_strength()  local
284 	u8 gain = ves1820_readreg(state, 0x17);  in ves1820_read_signal_strength()
292 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_read_snr()  local
294 	u8 quality = ~ves1820_readreg(state, 0x18);  in ves1820_read_snr()
302 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_read_ucblocks()  local
304 	*ucblocks = ves1820_readreg(state, 0x13) & 0x7f;  in ves1820_read_ucblocks()
309 	ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);  in ves1820_read_ucblocks()
310 	ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);  in ves1820_read_ucblocks()
318 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_get_frontend()  local
322 	sync = ves1820_readreg(state, 0x11);  in ves1820_get_frontend()
323 	afc = ves1820_readreg(state, 0x19);  in ves1820_get_frontend()
330 	if (!state->config->invert) {  in ves1820_get_frontend()
331 		p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;  in ves1820_get_frontend()
333 		p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;  in ves1820_get_frontend()
336 	p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;  in ves1820_get_frontend()
349 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_sleep()  local
351 	ves1820_writereg(state, 0x1b, 0x02);	/* pdown ADC */  in ves1820_sleep()
352 	ves1820_writereg(state, 0x00, 0x80);	/* standby */  in ves1820_sleep()
368 	struct ves1820_state* state = fe->demodulator_priv;  in ves1820_release()  local
369 	kfree(state);  in ves1820_release()
378 	struct ves1820_state* state = NULL;  in ves1820_attach()  local
381 	state = kzalloc(sizeof(struct ves1820_state), GFP_KERNEL);  in ves1820_attach()
382 	if (state == NULL)  in ves1820_attach()
386 	state->reg0 = ves1820_inittab[0];  in ves1820_attach()
387 	state->config = config;  in ves1820_attach()
388 	state->i2c = i2c;  in ves1820_attach()
389 	state->pwm = pwm;  in ves1820_attach()
392 	if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)  in ves1820_attach()
396 		printk("ves1820: pwm=0x%02x\n", state->pwm);  in ves1820_attach()
399 	memcpy(&state->frontend.ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));  in ves1820_attach()
400 …state->frontend.ops.info.symbol_rate_min = (state->config->xin / 2) / 64;      /* SACLK/64 == (XIN…  in ves1820_attach()
401 	state->frontend.ops.info.symbol_rate_max = (state->config->xin / 2) / 4;       /* SACLK/4 */  in ves1820_attach()
402 	state->frontend.demodulator_priv = state;  in ves1820_attach()
404 	return &state->frontend;  in ves1820_attach()
407 	kfree(state);  in ves1820_attach()