Lines Matching refs:tda1004x_write_mask
173 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) in tda1004x_write_mask() function
214 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); in tda1004x_enable_tuner_i2c()
223 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); in tda1004x_disable_tuner_i2c()
378 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP in tda1004x_check_upload_ok()
410 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); in tda10045_fwupload()
411 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda10045_fwupload()
412 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda10045_fwupload()
500 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); in tda10046_fwupload()
504 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f); in tda10046_fwupload()
511 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0); in tda10046_fwupload()
559 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST in tda10046_fwupload()
626 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC in tda10045_init()
629 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10045_init()
630 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream in tda10045_init()
631 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal in tda10045_init()
632 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer in tda10045_init()
633 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset in tda10045_init()
634 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset in tda10045_init()
637 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits in tda10045_init()
638 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity in tda10045_init()
641 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); in tda10045_init()
657 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10046_init()
664 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
668 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
672 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities in tda10046_init()
678 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
682 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40); in tda10046_init()
683 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); in tda10046_init()
685 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80); in tda10046_init()
686 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10, in tda10046_init()
690 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on in tda10046_init()
715 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); in tda1004x_set_fe()
716 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); in tda1004x_set_fe()
717 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); in tda1004x_set_fe()
720 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); in tda1004x_set_fe()
743 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto in tda1004x_set_fe()
744 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */ in tda1004x_set_fe()
745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits in tda1004x_set_fe()
746 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits in tda1004x_set_fe()
748 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto in tda1004x_set_fe()
754 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); in tda1004x_set_fe()
760 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); in tda1004x_set_fe()
765 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); in tda1004x_set_fe()
769 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); in tda1004x_set_fe()
773 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); in tda1004x_set_fe()
783 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); in tda1004x_set_fe()
787 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); in tda1004x_set_fe()
791 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); in tda1004x_set_fe()
795 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); in tda1004x_set_fe()
820 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); in tda1004x_set_fe()
824 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); in tda1004x_set_fe()
834 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
835 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
839 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
840 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); in tda1004x_set_fe()
844 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
845 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); in tda1004x_set_fe()
849 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
850 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); in tda1004x_set_fe()
854 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); in tda1004x_set_fe()
855 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
865 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
866 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); in tda1004x_set_fe()
870 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
871 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); in tda1004x_set_fe()
875 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); in tda1004x_set_fe()
876 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); in tda1004x_set_fe()
886 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda1004x_set_fe()
887 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda1004x_set_fe()
891 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); in tda1004x_set_fe()
893 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1); in tda1004x_set_fe()
1151 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1152 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1153 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1202 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); in tda1004x_sleep()
1211 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, in tda1004x_sleep()
1214 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0); in tda1004x_sleep()
1215 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); in tda1004x_sleep()