Lines Matching refs:ret
66 int ret; in mt312_read() local
79 ret = i2c_transfer(state->i2c, msg, 2); in mt312_read()
81 if (ret != 2) { in mt312_read()
82 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); in mt312_read()
100 int ret; in mt312_write() local
126 ret = i2c_transfer(state->i2c, &msg, 1); in mt312_write()
128 if (ret != 1) { in mt312_write()
129 dprintk("%s: ret == %d\n", __func__, ret); in mt312_write()
161 int ret; in mt312_get_inversion() local
164 ret = mt312_readreg(state, VIT_MODE, &vit_mode); in mt312_get_inversion()
165 if (ret < 0) in mt312_get_inversion()
166 return ret; in mt312_get_inversion()
176 int ret; in mt312_get_symbol_rate() local
183 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); in mt312_get_symbol_rate()
184 if (ret < 0) in mt312_get_symbol_rate()
185 return ret; in mt312_get_symbol_rate()
189 ret = mt312_writereg(state, MON_CTRL, 0x03); in mt312_get_symbol_rate()
190 if (ret < 0) in mt312_get_symbol_rate()
191 return ret; in mt312_get_symbol_rate()
193 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
194 if (ret < 0) in mt312_get_symbol_rate()
195 return ret; in mt312_get_symbol_rate()
202 ret = mt312_writereg(state, MON_CTRL, 0x05); in mt312_get_symbol_rate()
203 if (ret < 0) in mt312_get_symbol_rate()
204 return ret; in mt312_get_symbol_rate()
206 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
207 if (ret < 0) in mt312_get_symbol_rate()
208 return ret; in mt312_get_symbol_rate()
212 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
213 if (ret < 0) in mt312_get_symbol_rate()
214 return ret; in mt312_get_symbol_rate()
234 int ret; in mt312_get_code_rate() local
237 ret = mt312_readreg(state, FEC_STATUS, &fec_status); in mt312_get_code_rate()
238 if (ret < 0) in mt312_get_code_rate()
239 return ret; in mt312_get_code_rate()
249 int ret; in mt312_initfe() local
253 ret = mt312_writereg(state, CONFIG, in mt312_initfe()
255 if (ret < 0) in mt312_initfe()
256 return ret; in mt312_initfe()
262 ret = mt312_reset(state, 1); in mt312_initfe()
263 if (ret < 0) in mt312_initfe()
264 return ret; in mt312_initfe()
272 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); in mt312_initfe()
273 if (ret < 0) in mt312_initfe()
274 return ret; in mt312_initfe()
280 ret = mt312_writereg(state, GPP_CTRL, 0x80); in mt312_initfe()
281 if (ret < 0) in mt312_initfe()
282 return ret; in mt312_initfe()
287 ret = mt312_write(state, HW_CTRL, buf, 2); in mt312_initfe()
288 if (ret < 0) in mt312_initfe()
289 return ret; in mt312_initfe()
292 ret = mt312_writereg(state, HW_CTRL, 0x00); in mt312_initfe()
293 if (ret < 0) in mt312_initfe()
294 return ret; in mt312_initfe()
296 ret = mt312_writereg(state, MPEG_CTRL, 0x00); in mt312_initfe()
297 if (ret < 0) in mt312_initfe()
298 return ret; in mt312_initfe()
309 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); in mt312_initfe()
310 if (ret < 0) in mt312_initfe()
311 return ret; in mt312_initfe()
313 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); in mt312_initfe()
314 if (ret < 0) in mt312_initfe()
315 return ret; in mt312_initfe()
327 ret = mt312_writereg(state, OP_CTRL, buf[0]); in mt312_initfe()
328 if (ret < 0) in mt312_initfe()
329 return ret; in mt312_initfe()
335 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); in mt312_initfe()
336 if (ret < 0) in mt312_initfe()
337 return ret; in mt312_initfe()
339 ret = mt312_writereg(state, CS_SW_LIM, 0x69); in mt312_initfe()
340 if (ret < 0) in mt312_initfe()
341 return ret; in mt312_initfe()
350 int ret; in mt312_send_master_cmd() local
356 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_master_cmd()
357 if (ret < 0) in mt312_send_master_cmd()
358 return ret; in mt312_send_master_cmd()
360 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); in mt312_send_master_cmd()
361 if (ret < 0) in mt312_send_master_cmd()
362 return ret; in mt312_send_master_cmd()
364 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_master_cmd()
367 if (ret < 0) in mt312_send_master_cmd()
368 return ret; in mt312_send_master_cmd()
375 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); in mt312_send_master_cmd()
376 if (ret < 0) in mt312_send_master_cmd()
377 return ret; in mt312_send_master_cmd()
389 int ret; in mt312_send_burst() local
395 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_burst()
396 if (ret < 0) in mt312_send_burst()
397 return ret; in mt312_send_burst()
399 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_burst()
401 if (ret < 0) in mt312_send_burst()
402 return ret; in mt312_send_burst()
413 int ret; in mt312_set_tone() local
419 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_set_tone()
420 if (ret < 0) in mt312_set_tone()
421 return ret; in mt312_set_tone()
423 ret = mt312_writereg(state, DISEQC_MODE, in mt312_set_tone()
425 if (ret < 0) in mt312_set_tone()
426 return ret; in mt312_set_tone()
451 int ret; in mt312_read_status() local
456 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); in mt312_read_status()
457 if (ret < 0) in mt312_read_status()
458 return ret; in mt312_read_status()
480 int ret; in mt312_read_ber() local
483 ret = mt312_read(state, RS_BERCNT_H, buf, 3); in mt312_read_ber()
484 if (ret < 0) in mt312_read_ber()
485 return ret; in mt312_read_ber()
496 int ret; in mt312_read_signal_strength() local
501 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); in mt312_read_signal_strength()
502 if (ret < 0) in mt312_read_signal_strength()
503 return ret; in mt312_read_signal_strength()
518 int ret; in mt312_read_snr() local
521 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); in mt312_read_snr()
522 if (ret < 0) in mt312_read_snr()
523 return ret; in mt312_read_snr()
533 int ret; in mt312_read_ucblocks() local
536 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); in mt312_read_ucblocks()
537 if (ret < 0) in mt312_read_ucblocks()
538 return ret; in mt312_read_ucblocks()
549 int ret; in mt312_set_frontend() local
585 ret = mt312_readreg(state, CONFIG, &config_val); in mt312_set_frontend()
586 if (ret < 0) in mt312_set_frontend()
587 return ret; in mt312_set_frontend()
593 ret = mt312_initfe(fe); in mt312_set_frontend()
594 if (ret < 0) in mt312_set_frontend()
595 return ret; in mt312_set_frontend()
601 ret = mt312_initfe(fe); in mt312_set_frontend()
602 if (ret < 0) in mt312_set_frontend()
603 return ret; in mt312_set_frontend()
641 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); in mt312_set_frontend()
642 if (ret < 0) in mt312_set_frontend()
643 return ret; in mt312_set_frontend()
654 int ret; in mt312_get_frontend() local
656 ret = mt312_get_inversion(state, &p->inversion); in mt312_get_frontend()
657 if (ret < 0) in mt312_get_frontend()
658 return ret; in mt312_get_frontend()
660 ret = mt312_get_symbol_rate(state, &p->symbol_rate); in mt312_get_frontend()
661 if (ret < 0) in mt312_get_frontend()
662 return ret; in mt312_get_frontend()
664 ret = mt312_get_code_rate(state, &p->fec_inner); in mt312_get_frontend()
665 if (ret < 0) in mt312_get_frontend()
666 return ret; in mt312_get_frontend()
676 int ret; in mt312_i2c_gate_ctrl() local
680 ret = mt312_readreg(state, GPP_CTRL, &val); in mt312_i2c_gate_ctrl()
681 if (ret < 0) in mt312_i2c_gate_ctrl()
694 ret = mt312_writereg(state, GPP_CTRL, val); in mt312_i2c_gate_ctrl()
697 return ret; in mt312_i2c_gate_ctrl()
703 int ret; in mt312_sleep() local
707 ret = mt312_reset(state, 1); in mt312_sleep()
708 if (ret < 0) in mt312_sleep()
709 return ret; in mt312_sleep()
713 ret = mt312_writereg(state, GPP_CTRL, 0x00); in mt312_sleep()
714 if (ret < 0) in mt312_sleep()
715 return ret; in mt312_sleep()
718 ret = mt312_writereg(state, HW_CTRL, 0x0d); in mt312_sleep()
719 if (ret < 0) in mt312_sleep()
720 return ret; in mt312_sleep()
723 ret = mt312_readreg(state, CONFIG, &config); in mt312_sleep()
724 if (ret < 0) in mt312_sleep()
725 return ret; in mt312_sleep()
728 ret = mt312_writereg(state, CONFIG, config & 0x7f); in mt312_sleep()
729 if (ret < 0) in mt312_sleep()
730 return ret; in mt312_sleep()