Lines Matching refs:status
333 int status = 0; in WriteTable() local
338 while (!status) { in WriteTable()
351 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
354 return status; in WriteTable()
373 int status; in InitCE() local
377 status = WriteTable(state, state->m_InitCE); in InitCE()
378 if (status < 0) in InitCE()
386 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
387 if (status < 0) in InitCE()
390 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
391 if (status < 0) in InitCE()
394 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
395 if (status < 0) in InitCE()
398 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
399 if (status < 0) in InitCE()
404 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
405 if (status < 0) in InitCE()
408 return status; in InitCE()
413 int status = 0; in StopOC() local
421 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
422 if (status < 0) in StopOC()
429 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
430 if (status < 0) in StopOC()
432 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
433 if (status < 0) in StopOC()
435 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
436 if (status < 0) in StopOC()
438 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
439 if (status < 0) in StopOC()
443 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
444 if (status < 0) in StopOC()
446 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
447 if (status < 0) in StopOC()
452 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
453 if (status < 0) in StopOC()
458 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
459 if (status < 0) in StopOC()
464 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
465 if (status < 0) in StopOC()
467 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
468 if (status < 0) in StopOC()
470 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
471 if (status < 0) in StopOC()
475 return status; in StopOC()
480 int status = 0; in StartOC() local
484 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
485 if (status < 0) in StartOC()
489 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
490 if (status < 0) in StartOC()
492 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
493 if (status < 0) in StartOC()
497 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
498 if (status < 0) in StartOC()
502 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
503 if (status < 0) in StartOC()
506 return status; in StartOC()
541 int status; in DRX_GetLockStatus() local
545 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
546 if (status < 0) { in DRX_GetLockStatus()
547 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); in DRX_GetLockStatus()
548 return status; in DRX_GetLockStatus()
571 int status; in SetCfgIfAgc() local
581 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
582 if (status < 0) in SetCfgIfAgc()
586 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
587 if (status < 0) in SetCfgIfAgc()
592 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
593 if (status < 0) in SetCfgIfAgc()
610 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
611 if (status < 0) in SetCfgIfAgc()
616 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
617 if (status < 0) in SetCfgIfAgc()
624 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
625 if (status < 0) in SetCfgIfAgc()
635 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
636 if (status < 0) in SetCfgIfAgc()
638 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
639 if (status < 0) in SetCfgIfAgc()
686 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
687 if (status < 0) in SetCfgIfAgc()
689 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
690 if (status < 0) in SetCfgIfAgc()
692 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
693 if (status < 0) in SetCfgIfAgc()
695 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
696 if (status < 0) in SetCfgIfAgc()
698 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
699 if (status < 0) in SetCfgIfAgc()
709 return status; in SetCfgIfAgc()
714 int status = 0; in SetCfgRfAgc() local
727 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
728 if (status < 0) in SetCfgRfAgc()
737 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
738 if (status < 0) in SetCfgRfAgc()
741 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
742 if (status < 0) in SetCfgRfAgc()
748 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
749 if (status < 0) in SetCfgRfAgc()
755 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
756 if (status < 0) in SetCfgRfAgc()
762 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
763 if (status < 0) in SetCfgRfAgc()
779 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
780 if (status < 0) in SetCfgRfAgc()
783 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
784 if (status < 0) in SetCfgRfAgc()
790 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
791 if (status < 0) in SetCfgRfAgc()
796 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
797 if (status < 0) in SetCfgRfAgc()
807 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
808 if (status < 0) in SetCfgRfAgc()
814 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
815 if (status < 0) in SetCfgRfAgc()
830 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
831 if (status < 0) in SetCfgRfAgc()
834 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
835 if (status < 0) in SetCfgRfAgc()
841 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
842 if (status < 0) in SetCfgRfAgc()
848 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
849 if (status < 0) in SetCfgRfAgc()
855 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
856 if (status < 0) in SetCfgRfAgc()
861 return status; in SetCfgRfAgc()
866 int status = 0; in ReadIFAgc() local
871 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
873 if (status >= 0) { in ReadIFAgc()
901 return status; in ReadIFAgc()
933 int i, status = 0; in DownloadMicrocode() local
964 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
966 if (status < 0) in DownloadMicrocode()
972 return status; in DownloadMicrocode()
979 int status; in HI_Command() local
981 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
982 if (status < 0) in HI_Command()
983 return status; in HI_Command()
988 status = -1; in HI_Command()
991 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); in HI_Command()
994 if (status >= 0) in HI_Command()
995 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
996 return status; in HI_Command()
1001 int status = 0; in HI_CfgCommand() local
1014 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
1017 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); in HI_CfgCommand()
1019 return status; in HI_CfgCommand()
1032 int status; in HI_ResetCommand() local
1035 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1037 if (status == 0) in HI_ResetCommand()
1038 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); in HI_ResetCommand()
1041 return status; in HI_ResetCommand()
1064 int status;
1076 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1077 if (status < 0)
1079 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1080 if (status < 0)
1082 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1083 if (status < 0)
1085 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1086 if (status < 0)
1088 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1089 if (status < 0)
1092 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1093 if (status < 0)
1098 if (status >= 0) {
1102 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1104 if (status < 0)
1111 return status;
1118 int status;
1122 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1126 return status;
1170 int status = 0; in ResetECOD() local
1173 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1175 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1177 if (!(status < 0)) in ResetECOD()
1178 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1179 if (!(status < 0)) in ResetECOD()
1180 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1181 return status; in ResetECOD()
1188 int status; in SetCfgPga() local
1195 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1196 if (status < 0) in SetCfgPga()
1200 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1201 if (status < 0) in SetCfgPga()
1205 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1206 if (status < 0) in SetCfgPga()
1210 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1211 if (status < 0) in SetCfgPga()
1216 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1217 if (status < 0) in SetCfgPga()
1223 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1224 if (status < 0) in SetCfgPga()
1228 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1229 if (status < 0) in SetCfgPga()
1233 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1234 if (status < 0) in SetCfgPga()
1238 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1239 if (status < 0) in SetCfgPga()
1244 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1245 if (status < 0) in SetCfgPga()
1249 return status; in SetCfgPga()
1254 int status; in InitFE() local
1257 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1258 if (status < 0) in InitFE()
1262 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1267 status = SetCfgPga(state, 0); in InitFE()
1269 status = in InitFE()
1275 if (status < 0) in InitFE()
1277 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1278 if (status < 0) in InitFE()
1280 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1281 if (status < 0) in InitFE()
1284 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1285 if (status < 0) in InitFE()
1290 return status; in InitFE()
1308 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); in SC_WaitForReady() local
1309 if (status == 0 || curCmd == 0) in SC_WaitForReady()
1310 return status; in SC_WaitForReady()
1317 int status = 0; in SC_SendCommand() local
1327 status = -1; in SC_SendCommand()
1330 return status; in SC_SendCommand()
1336 int status = 0; in SC_ProcStartCommand() local
1343 status = -1; in SC_ProcStartCommand()
1354 return status; in SC_ProcStartCommand()
1360 int status; in SC_SetPrefParamCommand() local
1364 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1365 if (status < 0) in SC_SetPrefParamCommand()
1367 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1368 if (status < 0) in SC_SetPrefParamCommand()
1370 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1371 if (status < 0) in SC_SetPrefParamCommand()
1373 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1374 if (status < 0) in SC_SetPrefParamCommand()
1377 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1378 if (status < 0) in SC_SetPrefParamCommand()
1382 return status; in SC_SetPrefParamCommand()
1388 int status = 0;
1392 status = SC_WaitForReady(state);
1393 if (status < 0)
1395 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1396 if (status < 0)
1398 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1399 if (status < 0)
1403 return status;
1409 int status; in ConfigureMPEGOutput() local
1481 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1482 if (status < 0) in ConfigureMPEGOutput()
1484 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1485 if (status < 0) in ConfigureMPEGOutput()
1487 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1488 if (status < 0) in ConfigureMPEGOutput()
1490 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1491 if (status < 0) in ConfigureMPEGOutput()
1494 return status; in ConfigureMPEGOutput()
1499 int status = 0; in SetDeviceTypeId() local
1503 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1504 if (status < 0) in SetDeviceTypeId()
1507 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1508 if (status < 0) in SetDeviceTypeId()
1534 status = -1; in SetDeviceTypeId()
1540 if (status < 0) in SetDeviceTypeId()
1541 return status; in SetDeviceTypeId()
1586 return status; in SetDeviceTypeId()
1591 int status; in CorrectSysClockDeviation() local
1605 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1606 if (status < 0) in CorrectSysClockDeviation()
1608 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1609 if (status < 0) in CorrectSysClockDeviation()
1666 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1667 if (status < 0) in CorrectSysClockDeviation()
1671 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1672 if (status < 0) in CorrectSysClockDeviation()
1678 return status; in CorrectSysClockDeviation()
1683 int status; in DRX_Stop() local
1691 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1692 if (status < 0) in DRX_Stop()
1696 status = StopOC(state); in DRX_Stop()
1697 if (status < 0) in DRX_Stop()
1702 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1703 if (status < 0) in DRX_Stop()
1708 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1709 if (status < 0) in DRX_Stop()
1712 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1713 if (status < 0) in DRX_Stop()
1715 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1716 if (status < 0) in DRX_Stop()
1720 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1721 if (status < 0) in DRX_Stop()
1723 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1724 if (status < 0) in DRX_Stop()
1726 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1727 if (status < 0) in DRX_Stop()
1729 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1730 if (status < 0) in DRX_Stop()
1732 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1733 if (status < 0) in DRX_Stop()
1735 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1736 if (status < 0) in DRX_Stop()
1738 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1739 if (status < 0) in DRX_Stop()
1744 return status; in DRX_Stop()
1750 int status;
1754 status = -1;
1759 status = 0;
1764 status = -1;
1770 status = WriteTable(state, state->m_InitDiversityFront);
1773 status = WriteTable(state, state->m_InitDiversityEnd);
1779 status = WriteTable(state, state->m_DisableDiversity);
1784 if (!status)
1786 return status;
1792 int status = 0; in StartDiversity() local
1797 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1798 if (status < 0) in StartDiversity()
1801 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1802 if (status < 0) in StartDiversity()
1805 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1806 if (status < 0) in StartDiversity()
1809 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1810 if (status < 0) in StartDiversity()
1814 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1815 if (status < 0) in StartDiversity()
1823 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1824 if (status < 0) in StartDiversity()
1828 return status; in StartDiversity()
1873 int status = 0; in SetCfgNoiseCalibration() local
1876 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1877 if (status < 0) in SetCfgNoiseCalibration()
1883 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1884 if (status < 0) in SetCfgNoiseCalibration()
1887 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1888 if (status < 0) in SetCfgNoiseCalibration()
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1893 if (status < 0) in SetCfgNoiseCalibration()
1895 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1896 if (status < 0) in SetCfgNoiseCalibration()
1901 return status; in SetCfgNoiseCalibration()
1907 int status; in DRX_Start() local
1937 status = ResetECOD(state); in DRX_Start()
1938 if (status < 0) in DRX_Start()
1941 status = InitSC(state); in DRX_Start()
1942 if (status < 0) in DRX_Start()
1945 status = InitFT(state); in DRX_Start()
1946 if (status < 0) in DRX_Start()
1948 status = InitCP(state); in DRX_Start()
1949 if (status < 0) in DRX_Start()
1951 status = InitCE(state); in DRX_Start()
1952 if (status < 0) in DRX_Start()
1954 status = InitEQ(state); in DRX_Start()
1955 if (status < 0) in DRX_Start()
1957 status = InitSC(state); in DRX_Start()
1958 if (status < 0) in DRX_Start()
1964 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1965 if (status < 0) in DRX_Start()
1967 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1968 if (status < 0) in DRX_Start()
1980 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1981 if (status < 0) in DRX_Start()
1991 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
1992 if (status < 0) in DRX_Start()
2025 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2026 if (status < 0) in DRX_Start()
2028 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2029 if (status < 0) in DRX_Start()
2055 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2056 if (status < 0) in DRX_Start()
2058 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2059 if (status < 0) in DRX_Start()
2084 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2085 if (status < 0) in DRX_Start()
2087 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2088 if (status < 0) in DRX_Start()
2116 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2117 if (status < 0) in DRX_Start()
2119 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2120 if (status < 0) in DRX_Start()
2143 status = status; in DRX_Start()
2144 if (status < 0) in DRX_Start()
2155 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2156 if (status < 0) in DRX_Start()
2158 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2159 if (status < 0) in DRX_Start()
2161 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2162 if (status < 0) in DRX_Start()
2164 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2165 if (status < 0) in DRX_Start()
2167 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2168 if (status < 0) in DRX_Start()
2171 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2172 if (status < 0) in DRX_Start()
2174 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2175 if (status < 0) in DRX_Start()
2177 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2178 if (status < 0) in DRX_Start()
2180 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2181 if (status < 0) in DRX_Start()
2188 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2189 if (status < 0) in DRX_Start()
2191 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2192 if (status < 0) in DRX_Start()
2194 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2195 if (status < 0) in DRX_Start()
2197 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2198 if (status < 0) in DRX_Start()
2200 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2201 if (status < 0) in DRX_Start()
2204 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2205 if (status < 0) in DRX_Start()
2207 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2208 if (status < 0) in DRX_Start()
2210 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2211 if (status < 0) in DRX_Start()
2213 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2214 if (status < 0) in DRX_Start()
2222 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2223 if (status < 0) in DRX_Start()
2225 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2226 if (status < 0) in DRX_Start()
2228 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2229 if (status < 0) in DRX_Start()
2231 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2232 if (status < 0) in DRX_Start()
2234 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2235 if (status < 0) in DRX_Start()
2238 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2239 if (status < 0) in DRX_Start()
2241 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2242 if (status < 0) in DRX_Start()
2244 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2245 if (status < 0) in DRX_Start()
2247 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2248 if (status < 0) in DRX_Start()
2254 status = status; in DRX_Start()
2255 if (status < 0) in DRX_Start()
2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2264 if (status < 0) in DRX_Start()
2269 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2270 if (status < 0) in DRX_Start()
2280 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2281 if (status < 0) in DRX_Start()
2290 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2291 if (status < 0) in DRX_Start()
2298 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2299 if (status < 0) in DRX_Start()
2306 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2307 if (status < 0) in DRX_Start()
2314 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2315 if (status < 0) in DRX_Start()
2320 status = status; in DRX_Start()
2321 if (status < 0) in DRX_Start()
2340 status = Write16(state, in DRX_Start()
2347 status = Write16(state, in DRX_Start()
2354 status = Write16(state, in DRX_Start()
2358 status = -EINVAL; in DRX_Start()
2360 if (status < 0) in DRX_Start()
2363 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2364 if (status < 0) in DRX_Start()
2369 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2370 if (status < 0) in DRX_Start()
2383 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2384 if (status < 0) in DRX_Start()
2388 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2389 if (status < 0) in DRX_Start()
2394 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2395 if (status < 0) in DRX_Start()
2406 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2407 if (status < 0) in DRX_Start()
2409 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2410 if (status < 0) in DRX_Start()
2420 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2421 if (status < 0) in DRX_Start()
2423 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2424 if (status < 0) in DRX_Start()
2435 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2436 if (status < 0) in DRX_Start()
2440 …status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2441 if (status < 0) in DRX_Start()
2444 status = StartOC(state); in DRX_Start()
2445 if (status < 0) in DRX_Start()
2449 status = StartDiversity(state); in DRX_Start()
2450 if (status < 0) in DRX_Start()
2457 return status; in DRX_Start()
2615 int status = 0; in DRXD_init() local
2626 status = SetDeviceTypeId(state); in DRXD_init()
2627 if (status < 0) in DRXD_init()
2632 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2633 if (status < 0) in DRXD_init()
2640 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2641 if (status < 0) in DRXD_init()
2645 status = HI_ResetCommand(state); in DRXD_init()
2646 if (status < 0) in DRXD_init()
2649 status = StopAllProcessors(state); in DRXD_init()
2650 if (status < 0) in DRXD_init()
2652 status = InitCC(state); in DRXD_init()
2653 if (status < 0) in DRXD_init()
2682 status = InitHI(state); in DRXD_init()
2683 if (status < 0) in DRXD_init()
2685 status = InitAtomicRead(state); in DRXD_init()
2686 if (status < 0) in DRXD_init()
2689 status = EnableAndResetMB(state); in DRXD_init()
2690 if (status < 0) in DRXD_init()
2693 status = ResetCEFR(state); in DRXD_init()
2694 if (status < 0) in DRXD_init()
2698 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2699 if (status < 0) in DRXD_init()
2702 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2703 if (status < 0) in DRXD_init()
2716 status = InitFE(state); in DRXD_init()
2717 if (status < 0) in DRXD_init()
2719 status = InitFT(state); in DRXD_init()
2720 if (status < 0) in DRXD_init()
2722 status = InitCP(state); in DRXD_init()
2723 if (status < 0) in DRXD_init()
2725 status = InitCE(state); in DRXD_init()
2726 if (status < 0) in DRXD_init()
2728 status = InitEQ(state); in DRXD_init()
2729 if (status < 0) in DRXD_init()
2731 status = InitEC(state); in DRXD_init()
2732 if (status < 0) in DRXD_init()
2734 status = InitSC(state); in DRXD_init()
2735 if (status < 0) in DRXD_init()
2738 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2739 if (status < 0) in DRXD_init()
2741 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2742 if (status < 0) in DRXD_init()
2746 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2747 if (status < 0) in DRXD_init()
2749 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2750 if (status < 0) in DRXD_init()
2761 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2762 if (status < 0) in DRXD_init()
2765 status = StopOC(state); in DRXD_init()
2766 if (status < 0) in DRXD_init()
2771 status = 0; in DRXD_init()
2773 return status; in DRXD_init()
2808 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status) in drxd_read_status() argument
2814 *status = 0; in drxd_read_status()
2818 *status |= FE_HAS_LOCK; in drxd_read_status()
2821 *status |= FE_HAS_LOCK; in drxd_read_status()
2824 *status |= FE_HAS_VITERBI | FE_HAS_SYNC; in drxd_read_status()
2826 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; in drxd_read_status()