1418 	int rc;  in drxdap_fasi_read_block()  local
1480 		rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,  in drxdap_fasi_read_block()
1482 		if (rc == 0)  in drxdap_fasi_read_block()
1483 			rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);  in drxdap_fasi_read_block()
1486 		rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,  in drxdap_fasi_read_block()
1492 	} while (datasize && rc == 0);  in drxdap_fasi_read_block()
1494 	return rc;  in drxdap_fasi_read_block()
1521 	int rc;  in drxdap_fasi_read_reg16()  local
1526 	rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);  in drxdap_fasi_read_reg16()
1528 	return rc;  in drxdap_fasi_read_reg16()
1554 	int rc;  in drxdap_fasi_read_reg32()  local
1559 	rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);  in drxdap_fasi_read_reg32()
1563 	return rc;  in drxdap_fasi_read_reg32()
1764 	int rc = -EIO;  in drxdap_fasi_read_modify_write_reg16()  local
1770 	rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);  in drxdap_fasi_read_modify_write_reg16()
1771 	if (rc == 0)  in drxdap_fasi_read_modify_write_reg16()
1772 		rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);  in drxdap_fasi_read_modify_write_reg16()
1775 	return rc;  in drxdap_fasi_read_modify_write_reg16()
1837 	int rc;  in drxj_dap_rm_write_reg16short()  local
1843 	rc = drxdap_fasi_write_reg16(dev_addr,  in drxj_dap_rm_write_reg16short()
1847 	if (rc == 0) {  in drxj_dap_rm_write_reg16short()
1849 		rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,  in drxj_dap_rm_write_reg16short()
1852 	if (rc == 0) {  in drxj_dap_rm_write_reg16short()
1854 		rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,  in drxj_dap_rm_write_reg16short()
1857 	if (rc == 0) {  in drxj_dap_rm_write_reg16short()
1859 		rc = drxdap_fasi_write_reg16(dev_addr,  in drxj_dap_rm_write_reg16short()
1864 	return rc;  in drxj_dap_rm_write_reg16short()
2105 	int rc;  in drxj_dap_atomic_read_write_block()  local
2142 	rc = hi_command(dev_addr, &hi_cmd, &dummy);  in drxj_dap_atomic_read_write_block()
2143 	if (rc != 0) {  in drxj_dap_atomic_read_write_block()
2144 		pr_err("error %d\n", rc);  in drxj_dap_atomic_read_write_block()
2162 	return rc;  in drxj_dap_atomic_read_write_block()
2178 	int rc = -EIO;  in drxj_dap_atomic_read_reg32()  local
2184 	rc = drxj_dap_atomic_read_write_block(dev_addr, addr,  in drxj_dap_atomic_read_reg32()
2187 	if (rc < 0)  in drxj_dap_atomic_read_reg32()
2200 	return rc;  in drxj_dap_atomic_read_reg32()
2231 	int rc;  in hi_cfg_command()  local
2243 	rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);  in hi_cfg_command()
2244 	if (rc != 0) {  in hi_cfg_command()
2245 		pr_err("error %d\n", rc);  in hi_cfg_command()
2255 	return rc;  in hi_cfg_command()
2275 	int rc;  in hi_command()  local
2282 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);  in hi_command()
2283 		if (rc != 0) {  in hi_command()
2284 			pr_err("error %d\n", rc);  in hi_command()
2287 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);  in hi_command()
2288 		if (rc != 0) {  in hi_command()
2289 			pr_err("error %d\n", rc);  in hi_command()
2292 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);  in hi_command()
2293 		if (rc != 0) {  in hi_command()
2294 			pr_err("error %d\n", rc);  in hi_command()
2297 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);  in hi_command()
2298 		if (rc != 0) {  in hi_command()
2299 			pr_err("error %d\n", rc);  in hi_command()
2304 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);  in hi_command()
2305 		if (rc != 0) {  in hi_command()
2306 			pr_err("error %d\n", rc);  in hi_command()
2309 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);  in hi_command()
2310 		if (rc != 0) {  in hi_command()
2311 			pr_err("error %d\n", rc);  in hi_command()
2325 	rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);  in hi_command()
2326 	if (rc != 0) {  in hi_command()
2327 		pr_err("error %d\n", rc);  in hi_command()
2348 			rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);  in hi_command()
2349 			if (rc != 0) {  in hi_command()
2350 				pr_err("error %d\n", rc);  in hi_command()
2356 		rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);  in hi_command()
2357 		if (rc != 0) {  in hi_command()
2358 			pr_err("error %d\n", rc);  in hi_command()
2366 	return rc;  in hi_command()
2387 	int rc;  in init_hi()  local
2394 	rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);  in init_hi()
2395 	if (rc != 0) {  in init_hi()
2396 		pr_err("error %d\n", rc);  in init_hi()
2428 	rc = hi_cfg_command(demod);  in init_hi()
2429 	if (rc != 0) {  in init_hi()
2430 		pr_err("error %d\n", rc);  in init_hi()
2437 	return rc;  in init_hi()
2474 	int rc;  in get_device_capabilities()  local
2480 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in get_device_capabilities()
2481 	if (rc != 0) {  in get_device_capabilities()
2482 		pr_err("error %d\n", rc);  in get_device_capabilities()
2485 	rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);  in get_device_capabilities()
2486 	if (rc != 0) {  in get_device_capabilities()
2487 		pr_err("error %d\n", rc);  in get_device_capabilities()
2490 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);  in get_device_capabilities()
2491 	if (rc != 0) {  in get_device_capabilities()
2492 		pr_err("error %d\n", rc);  in get_device_capabilities()
2520 	rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);  in get_device_capabilities()
2521 	if (rc != 0) {  in get_device_capabilities()
2522 		pr_err("error %d\n", rc);  in get_device_capabilities()
2529 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in get_device_capabilities()
2530 		if (rc != 0) {  in get_device_capabilities()
2531 			pr_err("error %d\n", rc);  in get_device_capabilities()
2534 		rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);  in get_device_capabilities()
2535 		if (rc != 0) {  in get_device_capabilities()
2536 			pr_err("error %d\n", rc);  in get_device_capabilities()
2540 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);  in get_device_capabilities()
2541 		if (rc != 0) {  in get_device_capabilities()
2542 			pr_err("error %d\n", rc);  in get_device_capabilities()
2653 	return rc;  in get_device_capabilities()
2726 	int rc;  in ctrl_set_cfg_mpeg_output()  local
2762 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);  in ctrl_set_cfg_mpeg_output()
2763 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2764 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2769 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);  in ctrl_set_cfg_mpeg_output()
2770 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2771 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2774 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);  in ctrl_set_cfg_mpeg_output()
2775 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2776 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2779 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);  in ctrl_set_cfg_mpeg_output()
2780 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2781 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2784 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);  in ctrl_set_cfg_mpeg_output()
2785 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2786 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2789 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);  in ctrl_set_cfg_mpeg_output()
2790 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2791 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2794 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);  in ctrl_set_cfg_mpeg_output()
2795 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2796 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2800 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);  in ctrl_set_cfg_mpeg_output()
2801 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2802 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2806 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);  in ctrl_set_cfg_mpeg_output()
2807 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2808 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2839 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2840 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2841 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2844 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2845 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2846 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2849 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);  in ctrl_set_cfg_mpeg_output()
2850 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2851 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2854 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2855 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2856 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2859 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2860 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2861 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2865 				rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);  in ctrl_set_cfg_mpeg_output()
2866 				if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2867 					pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2871 				rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2872 				if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2873 					pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2877 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);  in ctrl_set_cfg_mpeg_output()
2878 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2879 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2882 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);  in ctrl_set_cfg_mpeg_output()
2883 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2884 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2893 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);  in ctrl_set_cfg_mpeg_output()
2894 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2895 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2898 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);  in ctrl_set_cfg_mpeg_output()
2899 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2900 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3055 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RAT…  in ctrl_set_cfg_mpeg_output()
3056 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3057 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3060 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RAT…  in ctrl_set_cfg_mpeg_output()
3061 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3062 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3065 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MO…  in ctrl_set_cfg_mpeg_output()
3066 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3067 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3070 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MO…  in ctrl_set_cfg_mpeg_output()
3071 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3072 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3075 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);  in ctrl_set_cfg_mpeg_output()
3076 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3077 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3082 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);  in ctrl_set_cfg_mpeg_output()
3083 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3084 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3089 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);  in ctrl_set_cfg_mpeg_output()
3090 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3091 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3094 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);  in ctrl_set_cfg_mpeg_output()
3095 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3096 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3101 		rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);  in ctrl_set_cfg_mpeg_output()
3102 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3103 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3108 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);  in ctrl_set_cfg_mpeg_output()
3109 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3110 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3113 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);  in ctrl_set_cfg_mpeg_output()
3114 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3115 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3118 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);  in ctrl_set_cfg_mpeg_output()
3119 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3120 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3126 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);  in ctrl_set_cfg_mpeg_output()
3127 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3128 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3132 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);  in ctrl_set_cfg_mpeg_output()
3133 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3134 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3137 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);  in ctrl_set_cfg_mpeg_output()
3138 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3139 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3142 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR…  in ctrl_set_cfg_mpeg_output()
3143 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3144 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3147 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);  in ctrl_set_cfg_mpeg_output()
3148 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3149 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3155 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3156 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3157 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3165 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3166 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3167 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3170 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3171 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3172 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3175 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3176 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3177 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3180 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3181 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3182 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3185 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3186 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3187 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3190 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3191 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3192 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3195 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3196 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3197 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3200 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3201 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3202 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3206 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3207 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3208 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3211 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3212 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3213 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3216 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3217 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3218 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3221 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3222 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3223 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3226 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3227 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3228 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3231 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3232 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3233 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3236 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3237 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3238 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3243 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3244 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3245 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3249 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3250 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3251 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3256 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);  in ctrl_set_cfg_mpeg_output()
3257 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3258 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3262 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3263 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3264 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3267 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3268 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3269 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3272 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3273 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3274 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3277 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3278 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3279 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3282 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3283 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3284 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3287 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3288 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3289 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3292 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3293 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3294 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3297 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3298 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3299 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3302 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3303 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3304 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3307 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3308 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3309 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3312 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3313 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3314 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3317 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3318 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3319 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3323 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3324 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3325 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3329 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3330 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3331 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3341 	return rc;  in ctrl_set_cfg_mpeg_output()
3368 	int rc;  in set_mpegtei_handling()  local
3376 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);  in set_mpegtei_handling()
3377 	if (rc != 0) {  in set_mpegtei_handling()
3378 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3381 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);  in set_mpegtei_handling()
3382 	if (rc != 0) {  in set_mpegtei_handling()
3383 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3386 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);  in set_mpegtei_handling()
3387 	if (rc != 0) {  in set_mpegtei_handling()
3388 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3406 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);  in set_mpegtei_handling()
3407 	if (rc != 0) {  in set_mpegtei_handling()
3408 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3411 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);  in set_mpegtei_handling()
3412 	if (rc != 0) {  in set_mpegtei_handling()
3413 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3416 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);  in set_mpegtei_handling()
3417 	if (rc != 0) {  in set_mpegtei_handling()
3418 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3424 	return rc;  in set_mpegtei_handling()
3441 	int rc;  in bit_reverse_mpeg_output()  local
3447 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);  in bit_reverse_mpeg_output()
3448 	if (rc != 0) {  in bit_reverse_mpeg_output()
3449 		pr_err("error %d\n", rc);  in bit_reverse_mpeg_output()
3459 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);  in bit_reverse_mpeg_output()
3460 	if (rc != 0) {  in bit_reverse_mpeg_output()
3461 		pr_err("error %d\n", rc);  in bit_reverse_mpeg_output()
3467 	return rc;  in bit_reverse_mpeg_output()
3485 	int rc;  in set_mpeg_start_width()  local
3494 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);  in set_mpeg_start_width()
3495 		if (rc != 0) {  in set_mpeg_start_width()
3496 			pr_err("error %d\n", rc);  in set_mpeg_start_width()
3502 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);  in set_mpeg_start_width()
3503 		if (rc != 0) {  in set_mpeg_start_width()
3504 			pr_err("error %d\n", rc);  in set_mpeg_start_width()
3511 	return rc;  in set_mpeg_start_width()
3531 	int rc;  in ctrl_set_uio_cfg()  local
3539 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in ctrl_set_uio_cfg()
3540 	if (rc != 0) {  in ctrl_set_uio_cfg()
3541 		pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3559 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3560 			if (rc != 0) {  in ctrl_set_uio_cfg()
3561 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3582 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3583 			if (rc != 0) {  in ctrl_set_uio_cfg()
3584 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3606 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3607 			if (rc != 0) {  in ctrl_set_uio_cfg()
3608 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3628 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3629 			if (rc != 0) {  in ctrl_set_uio_cfg()
3630 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3647 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_uio_cfg()
3648 	if (rc != 0) {  in ctrl_set_uio_cfg()
3649 		pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3655 	return rc;  in ctrl_set_uio_cfg()
3669 	int rc;  in ctrl_uio_write()  local
3679 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in ctrl_uio_write()
3680 	if (rc != 0) {  in ctrl_uio_write()
3681 		pr_err("error %d\n", rc);  in ctrl_uio_write()
3701 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3702 		if (rc != 0) {  in ctrl_uio_write()
3703 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3708 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);  in ctrl_uio_write()
3709 		if (rc != 0) {  in ctrl_uio_write()
3710 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3719 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);  in ctrl_uio_write()
3720 		if (rc != 0) {  in ctrl_uio_write()
3721 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3740 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3741 		if (rc != 0) {  in ctrl_uio_write()
3742 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3747 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);  in ctrl_uio_write()
3748 		if (rc != 0) {  in ctrl_uio_write()
3749 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3758 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);  in ctrl_uio_write()
3759 		if (rc != 0) {  in ctrl_uio_write()
3760 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3779 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3780 		if (rc != 0) {  in ctrl_uio_write()
3781 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3786 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);  in ctrl_uio_write()
3787 		if (rc != 0) {  in ctrl_uio_write()
3788 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3797 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);  in ctrl_uio_write()
3798 		if (rc != 0) {  in ctrl_uio_write()
3799 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3819 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3820 		if (rc != 0) {  in ctrl_uio_write()
3821 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3826 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);  in ctrl_uio_write()
3827 		if (rc != 0) {  in ctrl_uio_write()
3828 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3837 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);  in ctrl_uio_write()
3838 		if (rc != 0) {  in ctrl_uio_write()
3839 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3849 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_uio_write()
3850 	if (rc != 0) {  in ctrl_uio_write()
3851 		pr_err("error %d\n", rc);  in ctrl_uio_write()
3857 	return rc;  in ctrl_uio_write()
3914 	int rc;  in smart_ant_init()  local
3921 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in smart_ant_init()
3922 	if (rc != 0) {  in smart_ant_init()
3923 		pr_err("error %d\n", rc);  in smart_ant_init()
3927 	rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);  in smart_ant_init()
3928 	if (rc != 0) {  in smart_ant_init()
3929 		pr_err("error %d\n", rc);  in smart_ant_init()
3933 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) …  in smart_ant_init()
3934 		if (rc != 0) {  in smart_ant_init()
3935 			pr_err("error %d\n", rc);  in smart_ant_init()
3939 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M…  in smart_ant_init()
3940 		if (rc != 0) {  in smart_ant_init()
3941 			pr_err("error %d\n", rc);  in smart_ant_init()
3947 	rc = ctrl_set_uio_cfg(demod, &uio_cfg);  in smart_ant_init()
3948 	if (rc != 0) {  in smart_ant_init()
3949 		pr_err("error %d\n", rc);  in smart_ant_init()
3952 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);  in smart_ant_init()
3953 	if (rc != 0) {  in smart_ant_init()
3954 		pr_err("error %d\n", rc);  in smart_ant_init()
3957 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);  in smart_ant_init()
3958 	if (rc != 0) {  in smart_ant_init()
3959 		pr_err("error %d\n", rc);  in smart_ant_init()
3964 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in smart_ant_init()
3965 	if (rc != 0) {  in smart_ant_init()
3966 		pr_err("error %d\n", rc);  in smart_ant_init()
3972 	return rc;  in smart_ant_init()
3977 	int rc;  in scu_command()  local
3986 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);  in scu_command()
3987 	if (rc != 0) {  in scu_command()
3988 		pr_err("error %d\n", rc);  in scu_command()
3996 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);  in scu_command()
3997 		if (rc != 0) {  in scu_command()
3998 			pr_err("error %d\n", rc);  in scu_command()
4002 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);  in scu_command()
4003 		if (rc != 0) {  in scu_command()
4004 			pr_err("error %d\n", rc);  in scu_command()
4008 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);  in scu_command()
4009 		if (rc != 0) {  in scu_command()
4010 			pr_err("error %d\n", rc);  in scu_command()
4014 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);  in scu_command()
4015 		if (rc != 0) {  in scu_command()
4016 			pr_err("error %d\n", rc);  in scu_command()
4020 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);  in scu_command()
4021 		if (rc != 0) {  in scu_command()
4022 			pr_err("error %d\n", rc);  in scu_command()
4032 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);  in scu_command()
4033 	if (rc != 0) {  in scu_command()
4034 		pr_err("error %d\n", rc);  in scu_command()
4041 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);  in scu_command()
4042 		if (rc != 0) {  in scu_command()
4043 			pr_err("error %d\n", rc);  in scu_command()
4060 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);  in scu_command()
4061 			if (rc != 0) {  in scu_command()
4062 				pr_err("error %d\n", rc);  in scu_command()
4066 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);  in scu_command()
4067 			if (rc != 0) {  in scu_command()
4068 				pr_err("error %d\n", rc);  in scu_command()
4072 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);  in scu_command()
4073 			if (rc != 0) {  in scu_command()
4074 				pr_err("error %d\n", rc);  in scu_command()
4078 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);  in scu_command()
4079 			if (rc != 0) {  in scu_command()
4080 				pr_err("error %d\n", rc);  in scu_command()
4112 	return rc;  in scu_command()
4133 	int rc;  in drxj_dap_scu_atomic_read_write_block()  local
4163 	rc = scu_command(dev_addr, &scu_cmd);  in drxj_dap_scu_atomic_read_write_block()
4164 	if (rc != 0) {  in drxj_dap_scu_atomic_read_write_block()
4165 		pr_err("error %d\n", rc);  in drxj_dap_scu_atomic_read_write_block()
4181 	return rc;  in drxj_dap_scu_atomic_read_write_block()
4197 	int rc = -EIO;  in drxj_dap_scu_atomic_read_reg16()  local
4203 	rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);  in drxj_dap_scu_atomic_read_reg16()
4204 	if (rc < 0)  in drxj_dap_scu_atomic_read_reg16()
4205 		return rc;  in drxj_dap_scu_atomic_read_reg16()
4211 	return rc;  in drxj_dap_scu_atomic_read_reg16()
4225 	int rc = -EIO;  in drxj_dap_scu_atomic_write_reg16()  local
4230 	rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);  in drxj_dap_scu_atomic_write_reg16()
4232 	return rc;  in drxj_dap_scu_atomic_write_reg16()
4248 	int rc;  in adc_sync_measurement()  local
4254 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);  in adc_sync_measurement()
4255 	if (rc != 0) {  in adc_sync_measurement()
4256 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4259 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);  in adc_sync_measurement()
4260 	if (rc != 0) {  in adc_sync_measurement()
4261 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4269 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);  in adc_sync_measurement()
4270 	if (rc != 0) {  in adc_sync_measurement()
4271 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4276 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);  in adc_sync_measurement()
4277 	if (rc != 0) {  in adc_sync_measurement()
4278 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4283 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);  in adc_sync_measurement()
4284 	if (rc != 0) {  in adc_sync_measurement()
4285 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4293 	return rc;  in adc_sync_measurement()
4311 	int rc;  in adc_synchronization()  local
4316 	rc = adc_sync_measurement(demod, &count);  in adc_synchronization()
4317 	if (rc != 0) {  in adc_synchronization()
4318 		pr_err("error %d\n", rc);  in adc_synchronization()
4326 		rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);  in adc_synchronization()
4327 		if (rc != 0) {  in adc_synchronization()
4328 			pr_err("error %d\n", rc);  in adc_synchronization()
4333 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);  in adc_synchronization()
4334 		if (rc != 0) {  in adc_synchronization()
4335 			pr_err("error %d\n", rc);  in adc_synchronization()
4339 		rc = adc_sync_measurement(demod, &count);  in adc_synchronization()
4340 		if (rc != 0) {  in adc_synchronization()
4341 			pr_err("error %d\n", rc);  in adc_synchronization()
4352 	return rc;  in adc_synchronization()
4378 	int rc;  in init_agc()  local
4412 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);  in init_agc()
4413 		if (rc != 0) {  in init_agc()
4414 			pr_err("error %d\n", rc);  in init_agc()
4417 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);  in init_agc()
4418 		if (rc != 0) {  in init_agc()
4419 			pr_err("error %d\n", rc);  in init_agc()
4422 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);  in init_agc()
4423 		if (rc != 0) {  in init_agc()
4424 			pr_err("error %d\n", rc);  in init_agc()
4427 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);  in init_agc()
4428 		if (rc != 0) {  in init_agc()
4429 			pr_err("error %d\n", rc);  in init_agc()
4432 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);  in init_agc()
4433 		if (rc != 0) {  in init_agc()
4434 			pr_err("error %d\n", rc);  in init_agc()
4437 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);  in init_agc()
4438 		if (rc != 0) {  in init_agc()
4439 			pr_err("error %d\n", rc);  in init_agc()
4442 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);  in init_agc()
4443 		if (rc != 0) {  in init_agc()
4444 			pr_err("error %d\n", rc);  in init_agc()
4447 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);  in init_agc()
4448 		if (rc != 0) {  in init_agc()
4449 			pr_err("error %d\n", rc);  in init_agc()
4452 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);  in init_agc()
4453 		if (rc != 0) {  in init_agc()
4454 			pr_err("error %d\n", rc);  in init_agc()
4457 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);  in init_agc()
4458 		if (rc != 0) {  in init_agc()
4459 			pr_err("error %d\n", rc);  in init_agc()
4462 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);  in init_agc()
4463 		if (rc != 0) {  in init_agc()
4464 			pr_err("error %d\n", rc);  in init_agc()
4467 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);  in init_agc()
4468 		if (rc != 0) {  in init_agc()
4469 			pr_err("error %d\n", rc);  in init_agc()
4472 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);  in init_agc()
4473 		if (rc != 0) {  in init_agc()
4474 			pr_err("error %d\n", rc);  in init_agc()
4495 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);  in init_agc()
4496 		if (rc != 0) {  in init_agc()
4497 			pr_err("error %d\n", rc);  in init_agc()
4500 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);  in init_agc()
4501 		if (rc != 0) {  in init_agc()
4502 			pr_err("error %d\n", rc);  in init_agc()
4505 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);  in init_agc()
4506 		if (rc != 0) {  in init_agc()
4507 			pr_err("error %d\n", rc);  in init_agc()
4510 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);  in init_agc()
4511 		if (rc != 0) {  in init_agc()
4512 			pr_err("error %d\n", rc);  in init_agc()
4515 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);  in init_agc()
4516 		if (rc != 0) {  in init_agc()
4517 			pr_err("error %d\n", rc);  in init_agc()
4520 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);  in init_agc()
4521 		if (rc != 0) {  in init_agc()
4522 			pr_err("error %d\n", rc);  in init_agc()
4525 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);  in init_agc()
4526 		if (rc != 0) {  in init_agc()
4527 			pr_err("error %d\n", rc);  in init_agc()
4530 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);  in init_agc()
4531 		if (rc != 0) {  in init_agc()
4532 			pr_err("error %d\n", rc);  in init_agc()
4535 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);  in init_agc()
4536 		if (rc != 0) {  in init_agc()
4537 			pr_err("error %d\n", rc);  in init_agc()
4540 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);  in init_agc()
4541 		if (rc != 0) {  in init_agc()
4542 			pr_err("error %d\n", rc);  in init_agc()
4547 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);  in init_agc()
4548 		if (rc != 0) {  in init_agc()
4549 			pr_err("error %d\n", rc);  in init_agc()
4553 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);  in init_agc()
4554 		if (rc != 0) {  in init_agc()
4555 			pr_err("error %d\n", rc);  in init_agc()
4559 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);  in init_agc()
4560 		if (rc != 0) {  in init_agc()
4561 			pr_err("error %d\n", rc);  in init_agc()
4571 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);  in init_agc()
4572 	if (rc != 0) {  in init_agc()
4573 		pr_err("error %d\n", rc);  in init_agc()
4576 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);  in init_agc()
4577 	if (rc != 0) {  in init_agc()
4578 		pr_err("error %d\n", rc);  in init_agc()
4581 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);  in init_agc()
4582 	if (rc != 0) {  in init_agc()
4583 		pr_err("error %d\n", rc);  in init_agc()
4586 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);  in init_agc()
4587 	if (rc != 0) {  in init_agc()
4588 		pr_err("error %d\n", rc);  in init_agc()
4591 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);  in init_agc()
4592 	if (rc != 0) {  in init_agc()
4593 		pr_err("error %d\n", rc);  in init_agc()
4596 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);  in init_agc()
4597 	if (rc != 0) {  in init_agc()
4598 		pr_err("error %d\n", rc);  in init_agc()
4601 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);  in init_agc()
4602 	if (rc != 0) {  in init_agc()
4603 		pr_err("error %d\n", rc);  in init_agc()
4606 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);  in init_agc()
4607 	if (rc != 0) {  in init_agc()
4608 		pr_err("error %d\n", rc);  in init_agc()
4611 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);  in init_agc()
4612 	if (rc != 0) {  in init_agc()
4613 		pr_err("error %d\n", rc);  in init_agc()
4616 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);  in init_agc()
4617 	if (rc != 0) {  in init_agc()
4618 		pr_err("error %d\n", rc);  in init_agc()
4621 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);  in init_agc()
4622 	if (rc != 0) {  in init_agc()
4623 		pr_err("error %d\n", rc);  in init_agc()
4626 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);  in init_agc()
4627 	if (rc != 0) {  in init_agc()
4628 		pr_err("error %d\n", rc);  in init_agc()
4631 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);  in init_agc()
4632 	if (rc != 0) {  in init_agc()
4633 		pr_err("error %d\n", rc);  in init_agc()
4636 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);  in init_agc()
4637 	if (rc != 0) {  in init_agc()
4638 		pr_err("error %d\n", rc);  in init_agc()
4641 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);  in init_agc()
4642 	if (rc != 0) {  in init_agc()
4643 		pr_err("error %d\n", rc);  in init_agc()
4646 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);  in init_agc()
4647 	if (rc != 0) {  in init_agc()
4648 		pr_err("error %d\n", rc);  in init_agc()
4651 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);  in init_agc()
4652 	if (rc != 0) {  in init_agc()
4653 		pr_err("error %d\n", rc);  in init_agc()
4656 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);  in init_agc()
4657 	if (rc != 0) {  in init_agc()
4658 		pr_err("error %d\n", rc);  in init_agc()
4661 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);  in init_agc()
4662 	if (rc != 0) {  in init_agc()
4663 		pr_err("error %d\n", rc);  in init_agc()
4666 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);  in init_agc()
4667 	if (rc != 0) {  in init_agc()
4668 		pr_err("error %d\n", rc);  in init_agc()
4671 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);  in init_agc()
4672 	if (rc != 0) {  in init_agc()
4673 		pr_err("error %d\n", rc);  in init_agc()
4676 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);  in init_agc()
4677 	if (rc != 0) {  in init_agc()
4678 		pr_err("error %d\n", rc);  in init_agc()
4681 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);  in init_agc()
4682 	if (rc != 0) {  in init_agc()
4683 		pr_err("error %d\n", rc);  in init_agc()
4686 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);  in init_agc()
4687 	if (rc != 0) {  in init_agc()
4688 		pr_err("error %d\n", rc);  in init_agc()
4691 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);  in init_agc()
4692 	if (rc != 0) {  in init_agc()
4693 		pr_err("error %d\n", rc);  in init_agc()
4696 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);  in init_agc()
4697 	if (rc != 0) {  in init_agc()
4698 		pr_err("error %d\n", rc);  in init_agc()
4710 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);  in init_agc()
4711 	if (rc != 0) {  in init_agc()
4712 		pr_err("error %d\n", rc);  in init_agc()
4715 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);  in init_agc()
4716 	if (rc != 0) {  in init_agc()
4717 		pr_err("error %d\n", rc);  in init_agc()
4722 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in init_agc()
4723 	if (rc != 0) {  in init_agc()
4724 		pr_err("error %d\n", rc);  in init_agc()
4729 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in init_agc()
4730 	if (rc != 0) {  in init_agc()
4731 		pr_err("error %d\n", rc);  in init_agc()
4737 	return rc;  in init_agc()
4754 	int rc;  in set_frequency()  local
4824 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);  in set_frequency()
4825 	if (rc != 0) {  in set_frequency()
4826 		pr_err("error %d\n", rc);  in set_frequency()
4834 	return rc;  in set_frequency()
4850 	int rc;  in get_acc_pkt_err()  local
4860 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);  in get_acc_pkt_err()
4861 	if (rc != 0) {  in get_acc_pkt_err()
4862 		pr_err("error %d\n", rc);  in get_acc_pkt_err()
4882 	return rc;  in get_acc_pkt_err()
4903 	int rc;  in set_agc_rf()  local
4931 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_rf()
4932 			if (rc != 0) {  in set_agc_rf()
4933 				pr_err("error %d\n", rc);  in set_agc_rf()
4937 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_rf()
4938 			if (rc != 0) {  in set_agc_rf()
4939 				pr_err("error %d\n", rc);  in set_agc_rf()
4944 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_rf()
4945 			if (rc != 0) {  in set_agc_rf()
4946 				pr_err("error %d\n", rc);  in set_agc_rf()
4961 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_rf()
4962 			if (rc != 0) {  in set_agc_rf()
4963 				pr_err("error %d\n", rc);  in set_agc_rf()
4968 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);  in set_agc_rf()
4969 			if (rc != 0) {  in set_agc_rf()
4970 				pr_err("error %d\n", rc);  in set_agc_rf()
4974 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG…  in set_agc_rf()
4975 			if (rc != 0) {  in set_agc_rf()
4976 				pr_err("error %d\n", rc);  in set_agc_rf()
4991 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);  in set_agc_rf()
4992 				if (rc != 0) {  in set_agc_rf()
4993 					pr_err("error %d\n", rc);  in set_agc_rf()
4996 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);  in set_agc_rf()
4997 				if (rc != 0) {  in set_agc_rf()
4998 					pr_err("error %d\n", rc);  in set_agc_rf()
5004 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);  in set_agc_rf()
5005 			if (rc != 0) {  in set_agc_rf()
5006 				pr_err("error %d\n", rc);  in set_agc_rf()
5013 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_rf()
5014 			if (rc != 0) {  in set_agc_rf()
5015 				pr_err("error %d\n", rc);  in set_agc_rf()
5019 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_rf()
5020 			if (rc != 0) {  in set_agc_rf()
5021 				pr_err("error %d\n", rc);  in set_agc_rf()
5026 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_rf()
5027 			if (rc != 0) {  in set_agc_rf()
5028 				pr_err("error %d\n", rc);  in set_agc_rf()
5036 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_rf()
5037 			if (rc != 0) {  in set_agc_rf()
5038 				pr_err("error %d\n", rc);  in set_agc_rf()
5043 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);  in set_agc_rf()
5044 			if (rc != 0) {  in set_agc_rf()
5045 				pr_err("error %d\n", rc);  in set_agc_rf()
5052 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_rf()
5053 			if (rc != 0) {  in set_agc_rf()
5054 				pr_err("error %d\n", rc);  in set_agc_rf()
5058 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_rf()
5059 			if (rc != 0) {  in set_agc_rf()
5060 				pr_err("error %d\n", rc);  in set_agc_rf()
5065 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_rf()
5066 			if (rc != 0) {  in set_agc_rf()
5067 				pr_err("error %d\n", rc);  in set_agc_rf()
5071 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_rf()
5072 			if (rc != 0) {  in set_agc_rf()
5073 				pr_err("error %d\n", rc);  in set_agc_rf()
5100 	return rc;  in set_agc_rf()
5119 	int rc;  in set_agc_if()  local
5144 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_if()
5145 			if (rc != 0) {  in set_agc_if()
5146 				pr_err("error %d\n", rc);  in set_agc_if()
5150 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_if()
5151 			if (rc != 0) {  in set_agc_if()
5152 				pr_err("error %d\n", rc);  in set_agc_if()
5157 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_if()
5158 			if (rc != 0) {  in set_agc_if()
5159 				pr_err("error %d\n", rc);  in set_agc_if()
5175 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_if()
5176 			if (rc != 0) {  in set_agc_if()
5177 				pr_err("error %d\n", rc);  in set_agc_if()
5182 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);  in set_agc_if()
5183 			if (rc != 0) {  in set_agc_if()
5184 				pr_err("error %d\n", rc);  in set_agc_if()
5188 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA…  in set_agc_if()
5189 			if (rc != 0) {  in set_agc_if()
5190 				pr_err("error %d\n", rc);  in set_agc_if()
5205 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);  in set_agc_if()
5206 				if (rc != 0) {  in set_agc_if()
5207 					pr_err("error %d\n", rc);  in set_agc_if()
5210 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);  in set_agc_if()
5211 				if (rc != 0) {  in set_agc_if()
5212 					pr_err("error %d\n", rc);  in set_agc_if()
5216 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);  in set_agc_if()
5217 				if (rc != 0) {  in set_agc_if()
5218 					pr_err("error %d\n", rc);  in set_agc_if()
5221 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);  in set_agc_if()
5222 				if (rc != 0) {  in set_agc_if()
5223 					pr_err("error %d\n", rc);  in set_agc_if()
5232 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_if()
5233 			if (rc != 0) {  in set_agc_if()
5234 				pr_err("error %d\n", rc);  in set_agc_if()
5238 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_if()
5239 			if (rc != 0) {  in set_agc_if()
5240 				pr_err("error %d\n", rc);  in set_agc_if()
5245 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_if()
5246 			if (rc != 0) {  in set_agc_if()
5247 				pr_err("error %d\n", rc);  in set_agc_if()
5256 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_if()
5257 			if (rc != 0) {  in set_agc_if()
5258 				pr_err("error %d\n", rc);  in set_agc_if()
5263 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);  in set_agc_if()
5264 			if (rc != 0) {  in set_agc_if()
5265 				pr_err("error %d\n", rc);  in set_agc_if()
5273 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_if()
5274 			if (rc != 0) {  in set_agc_if()
5275 				pr_err("error %d\n", rc);  in set_agc_if()
5279 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_if()
5280 			if (rc != 0) {  in set_agc_if()
5281 				pr_err("error %d\n", rc);  in set_agc_if()
5286 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_if()
5287 			if (rc != 0) {  in set_agc_if()
5288 				pr_err("error %d\n", rc);  in set_agc_if()
5293 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_if()
5294 			if (rc != 0) {  in set_agc_if()
5295 				pr_err("error %d\n", rc);  in set_agc_if()
5304 		rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);  in set_agc_if()
5305 		if (rc != 0) {  in set_agc_if()
5306 			pr_err("error %d\n", rc);  in set_agc_if()
5329 	return rc;  in set_agc_if()
5343 	int rc;  in set_iqm_af()  local
5348 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_iqm_af()
5349 	if (rc != 0) {  in set_iqm_af()
5350 		pr_err("error %d\n", rc);  in set_iqm_af()
5357 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_iqm_af()
5358 	if (rc != 0) {  in set_iqm_af()
5359 		pr_err("error %d\n", rc);  in set_iqm_af()
5365 	return rc;  in set_iqm_af()
5395 	int rc;  in power_down_vsb()  local
5408 	rc = scu_command(dev_addr, &cmd_scu);  in power_down_vsb()
5409 	if (rc != 0) {  in power_down_vsb()
5410 		pr_err("error %d\n", rc);  in power_down_vsb()
5415 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in power_down_vsb()
5416 	if (rc != 0) {  in power_down_vsb()
5417 		pr_err("error %d\n", rc);  in power_down_vsb()
5420 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);  in power_down_vsb()
5421 	if (rc != 0) {  in power_down_vsb()
5422 		pr_err("error %d\n", rc);  in power_down_vsb()
5426 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);  in power_down_vsb()
5427 		if (rc != 0) {  in power_down_vsb()
5428 			pr_err("error %d\n", rc);  in power_down_vsb()
5431 		rc = set_iqm_af(demod, false);  in power_down_vsb()
5432 		if (rc != 0) {  in power_down_vsb()
5433 			pr_err("error %d\n", rc);  in power_down_vsb()
5437 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in power_down_vsb()
5438 		if (rc != 0) {  in power_down_vsb()
5439 			pr_err("error %d\n", rc);  in power_down_vsb()
5442 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in power_down_vsb()
5443 		if (rc != 0) {  in power_down_vsb()
5444 			pr_err("error %d\n", rc);  in power_down_vsb()
5447 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in power_down_vsb()
5448 		if (rc != 0) {  in power_down_vsb()
5449 			pr_err("error %d\n", rc);  in power_down_vsb()
5452 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in power_down_vsb()
5453 		if (rc != 0) {  in power_down_vsb()
5454 			pr_err("error %d\n", rc);  in power_down_vsb()
5457 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in power_down_vsb()
5458 		if (rc != 0) {  in power_down_vsb()
5459 			pr_err("error %d\n", rc);  in power_down_vsb()
5465 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in power_down_vsb()
5466 	if (rc != 0) {  in power_down_vsb()
5467 		pr_err("error %d\n", rc);  in power_down_vsb()
5473 	return rc;  in power_down_vsb()
5485 	int rc;  in set_vsb_leak_n_gain()  local
5676 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_g…  in set_vsb_leak_n_gain()
5677 	if (rc != 0) {  in set_vsb_leak_n_gain()
5678 		pr_err("error %d\n", rc);  in set_vsb_leak_n_gain()
5681 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_…  in set_vsb_leak_n_gain()
5682 	if (rc != 0) {  in set_vsb_leak_n_gain()
5683 		pr_err("error %d\n", rc);  in set_vsb_leak_n_gain()
5689 	return rc;  in set_vsb_leak_n_gain()
5702 	int rc;  in set_vsb()  local
5744 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in set_vsb()
5745 	if (rc != 0) {  in set_vsb()
5746 		pr_err("error %d\n", rc);  in set_vsb()
5749 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);  in set_vsb()
5750 	if (rc != 0) {  in set_vsb()
5751 		pr_err("error %d\n", rc);  in set_vsb()
5754 	rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in set_vsb()
5755 	if (rc != 0) {  in set_vsb()
5756 		pr_err("error %d\n", rc);  in set_vsb()
5759 	rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in set_vsb()
5760 	if (rc != 0) {  in set_vsb()
5761 		pr_err("error %d\n", rc);  in set_vsb()
5764 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in set_vsb()
5765 	if (rc != 0) {  in set_vsb()
5766 		pr_err("error %d\n", rc);  in set_vsb()
5769 	rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in set_vsb()
5770 	if (rc != 0) {  in set_vsb()
5771 		pr_err("error %d\n", rc);  in set_vsb()
5774 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in set_vsb()
5775 	if (rc != 0) {  in set_vsb()
5776 		pr_err("error %d\n", rc);  in set_vsb()
5787 	rc = scu_command(dev_addr, &cmd_scu);  in set_vsb()
5788 	if (rc != 0) {  in set_vsb()
5789 		pr_err("error %d\n", rc);  in set_vsb()
5793 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);  in set_vsb()
5794 	if (rc != 0) {  in set_vsb()
5795 		pr_err("error %d\n", rc);  in set_vsb()
5798 	rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);  in set_vsb()
5799 	if (rc != 0) {  in set_vsb()
5800 		pr_err("error %d\n", rc);  in set_vsb()
5803 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);  in set_vsb()
5804 	if (rc != 0) {  in set_vsb()
5805 		pr_err("error %d\n", rc);  in set_vsb()
5809 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);  in set_vsb()
5810 	if (rc != 0) {  in set_vsb()
5811 		pr_err("error %d\n", rc);  in set_vsb()
5814 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);  in set_vsb()
5815 	if (rc != 0) {  in set_vsb()
5816 		pr_err("error %d\n", rc);  in set_vsb()
5819 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);  in set_vsb()
5820 	if (rc != 0) {  in set_vsb()
5821 		pr_err("error %d\n", rc);  in set_vsb()
5825 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);  in set_vsb()
5826 	if (rc != 0) {  in set_vsb()
5827 		pr_err("error %d\n", rc);  in set_vsb()
5830 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);  in set_vsb()
5831 	if (rc != 0) {  in set_vsb()
5832 		pr_err("error %d\n", rc);  in set_vsb()
5835 	rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);  in set_vsb()
5836 	if (rc != 0) {  in set_vsb()
5837 		pr_err("error %d\n", rc);  in set_vsb()
5840 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);  in set_vsb()
5841 	if (rc != 0) {  in set_vsb()
5842 		pr_err("error %d\n", rc);  in set_vsb()
5845 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);  in set_vsb()
5846 	if (rc != 0) {  in set_vsb()
5847 		pr_err("error %d\n", rc);  in set_vsb()
5850 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);  in set_vsb()
5851 	if (rc != 0) {  in set_vsb()
5852 		pr_err("error %d\n", rc);  in set_vsb()
5855 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);  in set_vsb()
5856 	if (rc != 0) {  in set_vsb()
5857 		pr_err("error %d\n", rc);  in set_vsb()
5860 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);  in set_vsb()
5861 	if (rc != 0) {  in set_vsb()
5862 		pr_err("error %d\n", rc);  in set_vsb()
5865 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);  in set_vsb()
5866 	if (rc != 0) {  in set_vsb()
5867 		pr_err("error %d\n", rc);  in set_vsb()
5871 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)…  in set_vsb()
5872 	if (rc != 0) {  in set_vsb()
5873 		pr_err("error %d\n", rc);  in set_vsb()
5876 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)…  in set_vsb()
5877 	if (rc != 0) {  in set_vsb()
5878 		pr_err("error %d\n", rc);  in set_vsb()
5882 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);  in set_vsb()
5883 	if (rc != 0) {  in set_vsb()
5884 		pr_err("error %d\n", rc);  in set_vsb()
5887 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);  in set_vsb()
5888 	if (rc != 0) {  in set_vsb()
5889 		pr_err("error %d\n", rc);  in set_vsb()
5892 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);  in set_vsb()
5893 	if (rc != 0) {  in set_vsb()
5894 		pr_err("error %d\n", rc);  in set_vsb()
5897 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);  in set_vsb()
5898 	if (rc != 0) {  in set_vsb()
5899 		pr_err("error %d\n", rc);  in set_vsb()
5902 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);  in set_vsb()
5903 	if (rc != 0) {  in set_vsb()
5904 		pr_err("error %d\n", rc);  in set_vsb()
5907 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);  in set_vsb()
5908 	if (rc != 0) {  in set_vsb()
5909 		pr_err("error %d\n", rc);  in set_vsb()
5914 	rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);  in set_vsb()
5915 	if (rc != 0) {  in set_vsb()
5916 		pr_err("error %d\n", rc);  in set_vsb()
5921 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);  in set_vsb()
5922 		if (rc != 0) {  in set_vsb()
5923 			pr_err("error %d\n", rc);  in set_vsb()
5927 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_E…  in set_vsb()
5928 		if (rc != 0) {  in set_vsb()
5929 			pr_err("error %d\n", rc);  in set_vsb()
5935 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);  in set_vsb()
5936 	if (rc != 0) {  in set_vsb()
5937 		pr_err("error %d\n", rc);  in set_vsb()
5940 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);  in set_vsb()
5941 	if (rc != 0) {  in set_vsb()
5942 		pr_err("error %d\n", rc);  in set_vsb()
5945 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);  in set_vsb()
5946 	if (rc != 0) {  in set_vsb()
5947 		pr_err("error %d\n", rc);  in set_vsb()
5950 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);  in set_vsb()
5951 	if (rc != 0) {  in set_vsb()
5952 		pr_err("error %d\n", rc);  in set_vsb()
5958 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);  in set_vsb()
5959 		if (rc != 0) {  in set_vsb()
5960 			pr_err("error %d\n", rc);  in set_vsb()
5963 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__…  in set_vsb()
5964 		if (rc != 0) {  in set_vsb()
5965 			pr_err("error %d\n", rc);  in set_vsb()
5970 	rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);  in set_vsb()
5971 	if (rc != 0) {  in set_vsb()
5972 		pr_err("error %d\n", rc);  in set_vsb()
5975 	rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);  in set_vsb()
5976 	if (rc != 0) {  in set_vsb()
5977 		pr_err("error %d\n", rc);  in set_vsb()
5980 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);  in set_vsb()
5981 	if (rc != 0) {  in set_vsb()
5982 		pr_err("error %d\n", rc);  in set_vsb()
5986 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);  in set_vsb()
5987 	if (rc != 0) {  in set_vsb()
5988 		pr_err("error %d\n", rc);  in set_vsb()
5991 …rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0…  in set_vsb()
5992 	if (rc != 0) {  in set_vsb()
5993 		pr_err("error %d\n", rc);  in set_vsb()
5998 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);  in set_vsb()
5999 	if (rc != 0) {  in set_vsb()
6000 		pr_err("error %d\n", rc);  in set_vsb()
6003 	rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);  in set_vsb()
6004 	if (rc != 0) {  in set_vsb()
6005 		pr_err("error %d\n", rc);  in set_vsb()
6008 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);  in set_vsb()
6009 	if (rc != 0) {  in set_vsb()
6010 		pr_err("error %d\n", rc);  in set_vsb()
6013 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);  in set_vsb()
6014 	if (rc != 0) {  in set_vsb()
6015 		pr_err("error %d\n", rc);  in set_vsb()
6019 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);  in set_vsb()
6020 	if (rc != 0) {  in set_vsb()
6021 		pr_err("error %d\n", rc);  in set_vsb()
6026 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);  in set_vsb()
6027 		if (rc != 0) {  in set_vsb()
6028 			pr_err("error %d\n", rc);  in set_vsb()
6034 	rc = set_iqm_af(demod, true);  in set_vsb()
6035 	if (rc != 0) {  in set_vsb()
6036 		pr_err("error %d\n", rc);  in set_vsb()
6039 	rc = adc_synchronization(demod);  in set_vsb()
6040 	if (rc != 0) {  in set_vsb()
6041 		pr_err("error %d\n", rc);  in set_vsb()
6045 	rc = init_agc(demod);  in set_vsb()
6046 	if (rc != 0) {  in set_vsb()
6047 		pr_err("error %d\n", rc);  in set_vsb()
6050 	rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);  in set_vsb()
6051 	if (rc != 0) {  in set_vsb()
6052 		pr_err("error %d\n", rc);  in set_vsb()
6055 	rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);  in set_vsb()
6056 	if (rc != 0) {  in set_vsb()
6057 		pr_err("error %d\n", rc);  in set_vsb()
6066 		rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);  in set_vsb()
6067 		if (rc != 0) {  in set_vsb()
6068 			pr_err("error %d\n", rc);  in set_vsb()
6072 	rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));  in set_vsb()
6073 	if (rc != 0) {  in set_vsb()
6074 		pr_err("error %d\n", rc);  in set_vsb()
6079 	rc = set_mpegtei_handling(demod);  in set_vsb()
6080 	if (rc != 0) {  in set_vsb()
6081 		pr_err("error %d\n", rc);  in set_vsb()
6084 	rc = bit_reverse_mpeg_output(demod);  in set_vsb()
6085 	if (rc != 0) {  in set_vsb()
6086 		pr_err("error %d\n", rc);  in set_vsb()
6089 	rc = set_mpeg_start_width(demod);  in set_vsb()
6090 	if (rc != 0) {  in set_vsb()
6091 		pr_err("error %d\n", rc);  in set_vsb()
6102 		rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in set_vsb()
6103 		if (rc != 0) {  in set_vsb()
6104 			pr_err("error %d\n", rc);  in set_vsb()
6117 	rc = scu_command(dev_addr, &cmd_scu);  in set_vsb()
6118 	if (rc != 0) {  in set_vsb()
6119 		pr_err("error %d\n", rc);  in set_vsb()
6123 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);  in set_vsb()
6124 	if (rc != 0) {  in set_vsb()
6125 		pr_err("error %d\n", rc);  in set_vsb()
6128 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);  in set_vsb()
6129 	if (rc != 0) {  in set_vsb()
6130 		pr_err("error %d\n", rc);  in set_vsb()
6133 …rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_S…  in set_vsb()
6134 	if (rc != 0) {  in set_vsb()
6135 		pr_err("error %d\n", rc);  in set_vsb()
6138 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);  in set_vsb()
6139 	if (rc != 0) {  in set_vsb()
6140 		pr_err("error %d\n", rc);  in set_vsb()
6143 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);  in set_vsb()
6144 	if (rc != 0) {  in set_vsb()
6145 		pr_err("error %d\n", rc);  in set_vsb()
6148 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);  in set_vsb()
6149 	if (rc != 0) {  in set_vsb()
6150 		pr_err("error %d\n", rc);  in set_vsb()
6153 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);  in set_vsb()
6154 	if (rc != 0) {  in set_vsb()
6155 		pr_err("error %d\n", rc);  in set_vsb()
6158 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);  in set_vsb()
6159 	if (rc != 0) {  in set_vsb()
6160 		pr_err("error %d\n", rc);  in set_vsb()
6171 	rc = scu_command(dev_addr, &cmd_scu);  in set_vsb()
6172 	if (rc != 0) {  in set_vsb()
6173 		pr_err("error %d\n", rc);  in set_vsb()
6177 	rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);  in set_vsb()
6178 	if (rc != 0) {  in set_vsb()
6179 		pr_err("error %d\n", rc);  in set_vsb()
6182 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);  in set_vsb()
6183 	if (rc != 0) {  in set_vsb()
6184 		pr_err("error %d\n", rc);  in set_vsb()
6187 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);  in set_vsb()
6188 	if (rc != 0) {  in set_vsb()
6189 		pr_err("error %d\n", rc);  in set_vsb()
6195 	return rc;  in set_vsb()
6206 	int rc;  in get_vsb_post_rs_pck_err()  local
6213 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);  in get_vsb_post_rs_pck_err()
6214 	if (rc != 0) {  in get_vsb_post_rs_pck_err()
6215 		pr_err("error %d\n", rc);  in get_vsb_post_rs_pck_err()
6234 	return rc;  in get_vsb_post_rs_pck_err()
6245 	int rc;  in get_vs_bpost_viterbi_ber()  local
6252 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);  in get_vs_bpost_viterbi_ber()
6253 	if (rc != 0) {  in get_vs_bpost_viterbi_ber()
6254 		pr_err("error %d\n", rc);  in get_vs_bpost_viterbi_ber()
6279 	return rc;  in get_vs_bpost_viterbi_ber()
6291 	int rc;  in get_vs_bpre_viterbi_ber()  local
6293 	rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);  in get_vs_bpre_viterbi_ber()
6294 	if (rc != 0) {  in get_vs_bpre_viterbi_ber()
6295 		pr_err("error %d\n", rc);  in get_vs_bpre_viterbi_ber()
6311 	int rc;  in get_vsbmer()  local
6314 	rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);  in get_vsbmer()
6315 	if (rc != 0) {  in get_vsbmer()
6316 		pr_err("error %d\n", rc);  in get_vsbmer()
6324 	return rc;  in get_vsbmer()
6353 	int rc;  in power_down_qam()  local
6364 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in power_down_qam()
6365 	if (rc != 0) {  in power_down_qam()
6366 		pr_err("error %d\n", rc);  in power_down_qam()
6369 	rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);  in power_down_qam()
6370 	if (rc != 0) {  in power_down_qam()
6371 		pr_err("error %d\n", rc);  in power_down_qam()
6381 	rc = scu_command(dev_addr, &cmd_scu);  in power_down_qam()
6382 	if (rc != 0) {  in power_down_qam()
6383 		pr_err("error %d\n", rc);  in power_down_qam()
6388 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);  in power_down_qam()
6389 		if (rc != 0) {  in power_down_qam()
6390 			pr_err("error %d\n", rc);  in power_down_qam()
6393 		rc = set_iqm_af(demod, false);  in power_down_qam()
6394 		if (rc != 0) {  in power_down_qam()
6395 			pr_err("error %d\n", rc);  in power_down_qam()
6399 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in power_down_qam()
6400 		if (rc != 0) {  in power_down_qam()
6401 			pr_err("error %d\n", rc);  in power_down_qam()
6404 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in power_down_qam()
6405 		if (rc != 0) {  in power_down_qam()
6406 			pr_err("error %d\n", rc);  in power_down_qam()
6409 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in power_down_qam()
6410 		if (rc != 0) {  in power_down_qam()
6411 			pr_err("error %d\n", rc);  in power_down_qam()
6414 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in power_down_qam()
6415 		if (rc != 0) {  in power_down_qam()
6416 			pr_err("error %d\n", rc);  in power_down_qam()
6419 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in power_down_qam()
6420 		if (rc != 0) {  in power_down_qam()
6421 			pr_err("error %d\n", rc);  in power_down_qam()
6429 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in power_down_qam()
6430 	if (rc != 0) {  in power_down_qam()
6431 		pr_err("error %d\n", rc);  in power_down_qam()
6437 	return rc;  in power_down_qam()
6465 	int rc;  in set_qam_measurement()  local
6559 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);  in set_qam_measurement()
6560 	if (rc != 0) {  in set_qam_measurement()
6561 		pr_err("error %d\n", rc);  in set_qam_measurement()
6564 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);  in set_qam_measurement()
6565 	if (rc != 0) {  in set_qam_measurement()
6566 		pr_err("error %d\n", rc);  in set_qam_measurement()
6569 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);  in set_qam_measurement()
6570 	if (rc != 0) {  in set_qam_measurement()
6571 		pr_err("error %d\n", rc);  in set_qam_measurement()
6576 	rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);  in set_qam_measurement()
6577 	if (rc != 0) {  in set_qam_measurement()
6578 		pr_err("error %d\n", rc);  in set_qam_measurement()
6581 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);  in set_qam_measurement()
6582 	if (rc != 0) {  in set_qam_measurement()
6583 		pr_err("error %d\n", rc);  in set_qam_measurement()
6586 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);  in set_qam_measurement()
6587 	if (rc != 0) {  in set_qam_measurement()
6588 		pr_err("error %d\n", rc);  in set_qam_measurement()
6633 		rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);  in set_qam_measurement()
6634 		if (rc != 0) {  in set_qam_measurement()
6635 			pr_err("error %d\n", rc);  in set_qam_measurement()
6638 		rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);  in set_qam_measurement()
6639 		if (rc != 0) {  in set_qam_measurement()
6640 			pr_err("error %d\n", rc);  in set_qam_measurement()
6649 	return rc;  in set_qam_measurement()
6663 	int rc;  in set_qam16()  local
6681 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam16()
6682 	if (rc != 0) {  in set_qam16()
6683 		pr_err("error %d\n", rc);  in set_qam16()
6686 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam16()
6687 	if (rc != 0) {  in set_qam16()
6688 		pr_err("error %d\n", rc);  in set_qam16()
6692 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);  in set_qam16()
6693 	if (rc != 0) {  in set_qam16()
6694 		pr_err("error %d\n", rc);  in set_qam16()
6697 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);  in set_qam16()
6698 	if (rc != 0) {  in set_qam16()
6699 		pr_err("error %d\n", rc);  in set_qam16()
6702 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);  in set_qam16()
6703 	if (rc != 0) {  in set_qam16()
6704 		pr_err("error %d\n", rc);  in set_qam16()
6707 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);  in set_qam16()
6708 	if (rc != 0) {  in set_qam16()
6709 		pr_err("error %d\n", rc);  in set_qam16()
6712 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);  in set_qam16()
6713 	if (rc != 0) {  in set_qam16()
6714 		pr_err("error %d\n", rc);  in set_qam16()
6717 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);  in set_qam16()
6718 	if (rc != 0) {  in set_qam16()
6719 		pr_err("error %d\n", rc);  in set_qam16()
6723 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam16()
6724 	if (rc != 0) {  in set_qam16()
6725 		pr_err("error %d\n", rc);  in set_qam16()
6728 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);  in set_qam16()
6729 	if (rc != 0) {  in set_qam16()
6730 		pr_err("error %d\n", rc);  in set_qam16()
6733 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam16()
6734 	if (rc != 0) {  in set_qam16()
6735 		pr_err("error %d\n", rc);  in set_qam16()
6739 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);  in set_qam16()
6740 	if (rc != 0) {  in set_qam16()
6741 		pr_err("error %d\n", rc);  in set_qam16()
6744 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);  in set_qam16()
6745 	if (rc != 0) {  in set_qam16()
6746 		pr_err("error %d\n", rc);  in set_qam16()
6749 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);  in set_qam16()
6750 	if (rc != 0) {  in set_qam16()
6751 		pr_err("error %d\n", rc);  in set_qam16()
6754 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);  in set_qam16()
6755 	if (rc != 0) {  in set_qam16()
6756 		pr_err("error %d\n", rc);  in set_qam16()
6759 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);  in set_qam16()
6760 	if (rc != 0) {  in set_qam16()
6761 		pr_err("error %d\n", rc);  in set_qam16()
6764 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);  in set_qam16()
6765 	if (rc != 0) {  in set_qam16()
6766 		pr_err("error %d\n", rc);  in set_qam16()
6769 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);  in set_qam16()
6770 	if (rc != 0) {  in set_qam16()
6771 		pr_err("error %d\n", rc);  in set_qam16()
6775 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam16()
6776 	if (rc != 0) {  in set_qam16()
6777 		pr_err("error %d\n", rc);  in set_qam16()
6780 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam16()
6781 	if (rc != 0) {  in set_qam16()
6782 		pr_err("error %d\n", rc);  in set_qam16()
6785 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam16()
6786 	if (rc != 0) {  in set_qam16()
6787 		pr_err("error %d\n", rc);  in set_qam16()
6790 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);  in set_qam16()
6791 	if (rc != 0) {  in set_qam16()
6792 		pr_err("error %d\n", rc);  in set_qam16()
6795 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam16()
6796 	if (rc != 0) {  in set_qam16()
6797 		pr_err("error %d\n", rc);  in set_qam16()
6800 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam16()
6801 	if (rc != 0) {  in set_qam16()
6802 		pr_err("error %d\n", rc);  in set_qam16()
6805 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);  in set_qam16()
6806 	if (rc != 0) {  in set_qam16()
6807 		pr_err("error %d\n", rc);  in set_qam16()
6810 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);  in set_qam16()
6811 	if (rc != 0) {  in set_qam16()
6812 		pr_err("error %d\n", rc);  in set_qam16()
6815 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam16()
6816 	if (rc != 0) {  in set_qam16()
6817 		pr_err("error %d\n", rc);  in set_qam16()
6820 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam16()
6821 	if (rc != 0) {  in set_qam16()
6822 		pr_err("error %d\n", rc);  in set_qam16()
6825 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam16()
6826 	if (rc != 0) {  in set_qam16()
6827 		pr_err("error %d\n", rc);  in set_qam16()
6830 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam16()
6831 	if (rc != 0) {  in set_qam16()
6832 		pr_err("error %d\n", rc);  in set_qam16()
6835 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam16()
6836 	if (rc != 0) {  in set_qam16()
6837 		pr_err("error %d\n", rc);  in set_qam16()
6840 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam16()
6841 	if (rc != 0) {  in set_qam16()
6842 		pr_err("error %d\n", rc);  in set_qam16()
6845 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam16()
6846 	if (rc != 0) {  in set_qam16()
6847 		pr_err("error %d\n", rc);  in set_qam16()
6850 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);  in set_qam16()
6851 	if (rc != 0) {  in set_qam16()
6852 		pr_err("error %d\n", rc);  in set_qam16()
6855 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);  in set_qam16()
6856 	if (rc != 0) {  in set_qam16()
6857 		pr_err("error %d\n", rc);  in set_qam16()
6860 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam16()
6861 	if (rc != 0) {  in set_qam16()
6862 		pr_err("error %d\n", rc);  in set_qam16()
6865 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam16()
6866 	if (rc != 0) {  in set_qam16()
6867 		pr_err("error %d\n", rc);  in set_qam16()
6870 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);  in set_qam16()
6871 	if (rc != 0) {  in set_qam16()
6872 		pr_err("error %d\n", rc);  in set_qam16()
6876 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);  in set_qam16()
6877 	if (rc != 0) {  in set_qam16()
6878 		pr_err("error %d\n", rc);  in set_qam16()
6884 	return rc;  in set_qam16()
6898 	int rc;  in set_qam32()  local
6916 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam32()
6917 	if (rc != 0) {  in set_qam32()
6918 		pr_err("error %d\n", rc);  in set_qam32()
6921 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam32()
6922 	if (rc != 0) {  in set_qam32()
6923 		pr_err("error %d\n", rc);  in set_qam32()
6927 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);  in set_qam32()
6928 	if (rc != 0) {  in set_qam32()
6929 		pr_err("error %d\n", rc);  in set_qam32()
6932 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);  in set_qam32()
6933 	if (rc != 0) {  in set_qam32()
6934 		pr_err("error %d\n", rc);  in set_qam32()
6937 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam32()
6938 	if (rc != 0) {  in set_qam32()
6939 		pr_err("error %d\n", rc);  in set_qam32()
6942 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);  in set_qam32()
6943 	if (rc != 0) {  in set_qam32()
6944 		pr_err("error %d\n", rc);  in set_qam32()
6947 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam32()
6948 	if (rc != 0) {  in set_qam32()
6949 		pr_err("error %d\n", rc);  in set_qam32()
6952 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);  in set_qam32()
6953 	if (rc != 0) {  in set_qam32()
6954 		pr_err("error %d\n", rc);  in set_qam32()
6958 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam32()
6959 	if (rc != 0) {  in set_qam32()
6960 		pr_err("error %d\n", rc);  in set_qam32()
6963 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);  in set_qam32()
6964 	if (rc != 0) {  in set_qam32()
6965 		pr_err("error %d\n", rc);  in set_qam32()
6968 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam32()
6969 	if (rc != 0) {  in set_qam32()
6970 		pr_err("error %d\n", rc);  in set_qam32()
6974 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);  in set_qam32()
6975 	if (rc != 0) {  in set_qam32()
6976 		pr_err("error %d\n", rc);  in set_qam32()
6979 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);  in set_qam32()
6980 	if (rc != 0) {  in set_qam32()
6981 		pr_err("error %d\n", rc);  in set_qam32()
6984 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);  in set_qam32()
6985 	if (rc != 0) {  in set_qam32()
6986 		pr_err("error %d\n", rc);  in set_qam32()
6989 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);  in set_qam32()
6990 	if (rc != 0) {  in set_qam32()
6991 		pr_err("error %d\n", rc);  in set_qam32()
6994 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);  in set_qam32()
6995 	if (rc != 0) {  in set_qam32()
6996 		pr_err("error %d\n", rc);  in set_qam32()
6999 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);  in set_qam32()
7000 	if (rc != 0) {  in set_qam32()
7001 		pr_err("error %d\n", rc);  in set_qam32()
7004 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);  in set_qam32()
7005 	if (rc != 0) {  in set_qam32()
7006 		pr_err("error %d\n", rc);  in set_qam32()
7010 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam32()
7011 	if (rc != 0) {  in set_qam32()
7012 		pr_err("error %d\n", rc);  in set_qam32()
7015 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam32()
7016 	if (rc != 0) {  in set_qam32()
7017 		pr_err("error %d\n", rc);  in set_qam32()
7020 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam32()
7021 	if (rc != 0) {  in set_qam32()
7022 		pr_err("error %d\n", rc);  in set_qam32()
7025 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);  in set_qam32()
7026 	if (rc != 0) {  in set_qam32()
7027 		pr_err("error %d\n", rc);  in set_qam32()
7030 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam32()
7031 	if (rc != 0) {  in set_qam32()
7032 		pr_err("error %d\n", rc);  in set_qam32()
7035 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam32()
7036 	if (rc != 0) {  in set_qam32()
7037 		pr_err("error %d\n", rc);  in set_qam32()
7040 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);  in set_qam32()
7041 	if (rc != 0) {  in set_qam32()
7042 		pr_err("error %d\n", rc);  in set_qam32()
7045 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);  in set_qam32()
7046 	if (rc != 0) {  in set_qam32()
7047 		pr_err("error %d\n", rc);  in set_qam32()
7050 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam32()
7051 	if (rc != 0) {  in set_qam32()
7052 		pr_err("error %d\n", rc);  in set_qam32()
7055 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam32()
7056 	if (rc != 0) {  in set_qam32()
7057 		pr_err("error %d\n", rc);  in set_qam32()
7060 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam32()
7061 	if (rc != 0) {  in set_qam32()
7062 		pr_err("error %d\n", rc);  in set_qam32()
7065 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam32()
7066 	if (rc != 0) {  in set_qam32()
7067 		pr_err("error %d\n", rc);  in set_qam32()
7070 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam32()
7071 	if (rc != 0) {  in set_qam32()
7072 		pr_err("error %d\n", rc);  in set_qam32()
7075 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam32()
7076 	if (rc != 0) {  in set_qam32()
7077 		pr_err("error %d\n", rc);  in set_qam32()
7080 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam32()
7081 	if (rc != 0) {  in set_qam32()
7082 		pr_err("error %d\n", rc);  in set_qam32()
7085 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);  in set_qam32()
7086 	if (rc != 0) {  in set_qam32()
7087 		pr_err("error %d\n", rc);  in set_qam32()
7090 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);  in set_qam32()
7091 	if (rc != 0) {  in set_qam32()
7092 		pr_err("error %d\n", rc);  in set_qam32()
7095 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam32()
7096 	if (rc != 0) {  in set_qam32()
7097 		pr_err("error %d\n", rc);  in set_qam32()
7100 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam32()
7101 	if (rc != 0) {  in set_qam32()
7102 		pr_err("error %d\n", rc);  in set_qam32()
7105 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);  in set_qam32()
7106 	if (rc != 0) {  in set_qam32()
7107 		pr_err("error %d\n", rc);  in set_qam32()
7111 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);  in set_qam32()
7112 	if (rc != 0) {  in set_qam32()
7113 		pr_err("error %d\n", rc);  in set_qam32()
7119 	return rc;  in set_qam32()
7133 	int rc;  in set_qam64()  local
7151 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam64()
7152 	if (rc != 0) {  in set_qam64()
7153 		pr_err("error %d\n", rc);  in set_qam64()
7156 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam64()
7157 	if (rc != 0) {  in set_qam64()
7158 		pr_err("error %d\n", rc);  in set_qam64()
7162 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);  in set_qam64()
7163 	if (rc != 0) {  in set_qam64()
7164 		pr_err("error %d\n", rc);  in set_qam64()
7167 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);  in set_qam64()
7168 	if (rc != 0) {  in set_qam64()
7169 		pr_err("error %d\n", rc);  in set_qam64()
7172 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam64()
7173 	if (rc != 0) {  in set_qam64()
7174 		pr_err("error %d\n", rc);  in set_qam64()
7177 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);  in set_qam64()
7178 	if (rc != 0) {  in set_qam64()
7179 		pr_err("error %d\n", rc);  in set_qam64()
7182 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam64()
7183 	if (rc != 0) {  in set_qam64()
7184 		pr_err("error %d\n", rc);  in set_qam64()
7187 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);  in set_qam64()
7188 	if (rc != 0) {  in set_qam64()
7189 		pr_err("error %d\n", rc);  in set_qam64()
7193 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam64()
7194 	if (rc != 0) {  in set_qam64()
7195 		pr_err("error %d\n", rc);  in set_qam64()
7198 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);  in set_qam64()
7199 	if (rc != 0) {  in set_qam64()
7200 		pr_err("error %d\n", rc);  in set_qam64()
7203 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam64()
7204 	if (rc != 0) {  in set_qam64()
7205 		pr_err("error %d\n", rc);  in set_qam64()
7209 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);  in set_qam64()
7210 	if (rc != 0) {  in set_qam64()
7211 		pr_err("error %d\n", rc);  in set_qam64()
7214 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);  in set_qam64()
7215 	if (rc != 0) {  in set_qam64()
7216 		pr_err("error %d\n", rc);  in set_qam64()
7219 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);  in set_qam64()
7220 	if (rc != 0) {  in set_qam64()
7221 		pr_err("error %d\n", rc);  in set_qam64()
7224 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);  in set_qam64()
7225 	if (rc != 0) {  in set_qam64()
7226 		pr_err("error %d\n", rc);  in set_qam64()
7229 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);  in set_qam64()
7230 	if (rc != 0) {  in set_qam64()
7231 		pr_err("error %d\n", rc);  in set_qam64()
7234 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);  in set_qam64()
7235 	if (rc != 0) {  in set_qam64()
7236 		pr_err("error %d\n", rc);  in set_qam64()
7239 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);  in set_qam64()
7240 	if (rc != 0) {  in set_qam64()
7241 		pr_err("error %d\n", rc);  in set_qam64()
7245 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam64()
7246 	if (rc != 0) {  in set_qam64()
7247 		pr_err("error %d\n", rc);  in set_qam64()
7250 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam64()
7251 	if (rc != 0) {  in set_qam64()
7252 		pr_err("error %d\n", rc);  in set_qam64()
7255 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam64()
7256 	if (rc != 0) {  in set_qam64()
7257 		pr_err("error %d\n", rc);  in set_qam64()
7260 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);  in set_qam64()
7261 	if (rc != 0) {  in set_qam64()
7262 		pr_err("error %d\n", rc);  in set_qam64()
7265 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam64()
7266 	if (rc != 0) {  in set_qam64()
7267 		pr_err("error %d\n", rc);  in set_qam64()
7270 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam64()
7271 	if (rc != 0) {  in set_qam64()
7272 		pr_err("error %d\n", rc);  in set_qam64()
7275 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);  in set_qam64()
7276 	if (rc != 0) {  in set_qam64()
7277 		pr_err("error %d\n", rc);  in set_qam64()
7280 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);  in set_qam64()
7281 	if (rc != 0) {  in set_qam64()
7282 		pr_err("error %d\n", rc);  in set_qam64()
7285 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam64()
7286 	if (rc != 0) {  in set_qam64()
7287 		pr_err("error %d\n", rc);  in set_qam64()
7290 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam64()
7291 	if (rc != 0) {  in set_qam64()
7292 		pr_err("error %d\n", rc);  in set_qam64()
7295 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam64()
7296 	if (rc != 0) {  in set_qam64()
7297 		pr_err("error %d\n", rc);  in set_qam64()
7300 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam64()
7301 	if (rc != 0) {  in set_qam64()
7302 		pr_err("error %d\n", rc);  in set_qam64()
7305 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam64()
7306 	if (rc != 0) {  in set_qam64()
7307 		pr_err("error %d\n", rc);  in set_qam64()
7310 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam64()
7311 	if (rc != 0) {  in set_qam64()
7312 		pr_err("error %d\n", rc);  in set_qam64()
7315 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam64()
7316 	if (rc != 0) {  in set_qam64()
7317 		pr_err("error %d\n", rc);  in set_qam64()
7320 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);  in set_qam64()
7321 	if (rc != 0) {  in set_qam64()
7322 		pr_err("error %d\n", rc);  in set_qam64()
7325 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);  in set_qam64()
7326 	if (rc != 0) {  in set_qam64()
7327 		pr_err("error %d\n", rc);  in set_qam64()
7330 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam64()
7331 	if (rc != 0) {  in set_qam64()
7332 		pr_err("error %d\n", rc);  in set_qam64()
7335 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam64()
7336 	if (rc != 0) {  in set_qam64()
7337 		pr_err("error %d\n", rc);  in set_qam64()
7340 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);  in set_qam64()
7341 	if (rc != 0) {  in set_qam64()
7342 		pr_err("error %d\n", rc);  in set_qam64()
7346 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);  in set_qam64()
7347 	if (rc != 0) {  in set_qam64()
7348 		pr_err("error %d\n", rc);  in set_qam64()
7354 	return rc;  in set_qam64()
7368 	int rc;  in set_qam128()  local
7386 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam128()
7387 	if (rc != 0) {  in set_qam128()
7388 		pr_err("error %d\n", rc);  in set_qam128()
7391 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam128()
7392 	if (rc != 0) {  in set_qam128()
7393 		pr_err("error %d\n", rc);  in set_qam128()
7397 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);  in set_qam128()
7398 	if (rc != 0) {  in set_qam128()
7399 		pr_err("error %d\n", rc);  in set_qam128()
7402 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);  in set_qam128()
7403 	if (rc != 0) {  in set_qam128()
7404 		pr_err("error %d\n", rc);  in set_qam128()
7407 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam128()
7408 	if (rc != 0) {  in set_qam128()
7409 		pr_err("error %d\n", rc);  in set_qam128()
7412 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);  in set_qam128()
7413 	if (rc != 0) {  in set_qam128()
7414 		pr_err("error %d\n", rc);  in set_qam128()
7417 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam128()
7418 	if (rc != 0) {  in set_qam128()
7419 		pr_err("error %d\n", rc);  in set_qam128()
7422 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);  in set_qam128()
7423 	if (rc != 0) {  in set_qam128()
7424 		pr_err("error %d\n", rc);  in set_qam128()
7428 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam128()
7429 	if (rc != 0) {  in set_qam128()
7430 		pr_err("error %d\n", rc);  in set_qam128()
7433 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);  in set_qam128()
7434 	if (rc != 0) {  in set_qam128()
7435 		pr_err("error %d\n", rc);  in set_qam128()
7438 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam128()
7439 	if (rc != 0) {  in set_qam128()
7440 		pr_err("error %d\n", rc);  in set_qam128()
7444 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);  in set_qam128()
7445 	if (rc != 0) {  in set_qam128()
7446 		pr_err("error %d\n", rc);  in set_qam128()
7449 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);  in set_qam128()
7450 	if (rc != 0) {  in set_qam128()
7451 		pr_err("error %d\n", rc);  in set_qam128()
7454 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);  in set_qam128()
7455 	if (rc != 0) {  in set_qam128()
7456 		pr_err("error %d\n", rc);  in set_qam128()
7459 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);  in set_qam128()
7460 	if (rc != 0) {  in set_qam128()
7461 		pr_err("error %d\n", rc);  in set_qam128()
7464 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);  in set_qam128()
7465 	if (rc != 0) {  in set_qam128()
7466 		pr_err("error %d\n", rc);  in set_qam128()
7469 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);  in set_qam128()
7470 	if (rc != 0) {  in set_qam128()
7471 		pr_err("error %d\n", rc);  in set_qam128()
7474 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);  in set_qam128()
7475 	if (rc != 0) {  in set_qam128()
7476 		pr_err("error %d\n", rc);  in set_qam128()
7480 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam128()
7481 	if (rc != 0) {  in set_qam128()
7482 		pr_err("error %d\n", rc);  in set_qam128()
7485 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam128()
7486 	if (rc != 0) {  in set_qam128()
7487 		pr_err("error %d\n", rc);  in set_qam128()
7490 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam128()
7491 	if (rc != 0) {  in set_qam128()
7492 		pr_err("error %d\n", rc);  in set_qam128()
7495 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);  in set_qam128()
7496 	if (rc != 0) {  in set_qam128()
7497 		pr_err("error %d\n", rc);  in set_qam128()
7500 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam128()
7501 	if (rc != 0) {  in set_qam128()
7502 		pr_err("error %d\n", rc);  in set_qam128()
7505 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam128()
7506 	if (rc != 0) {  in set_qam128()
7507 		pr_err("error %d\n", rc);  in set_qam128()
7510 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);  in set_qam128()
7511 	if (rc != 0) {  in set_qam128()
7512 		pr_err("error %d\n", rc);  in set_qam128()
7515 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);  in set_qam128()
7516 	if (rc != 0) {  in set_qam128()
7517 		pr_err("error %d\n", rc);  in set_qam128()
7520 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam128()
7521 	if (rc != 0) {  in set_qam128()
7522 		pr_err("error %d\n", rc);  in set_qam128()
7525 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam128()
7526 	if (rc != 0) {  in set_qam128()
7527 		pr_err("error %d\n", rc);  in set_qam128()
7530 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam128()
7531 	if (rc != 0) {  in set_qam128()
7532 		pr_err("error %d\n", rc);  in set_qam128()
7535 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam128()
7536 	if (rc != 0) {  in set_qam128()
7537 		pr_err("error %d\n", rc);  in set_qam128()
7540 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam128()
7541 	if (rc != 0) {  in set_qam128()
7542 		pr_err("error %d\n", rc);  in set_qam128()
7545 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam128()
7546 	if (rc != 0) {  in set_qam128()
7547 		pr_err("error %d\n", rc);  in set_qam128()
7550 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam128()
7551 	if (rc != 0) {  in set_qam128()
7552 		pr_err("error %d\n", rc);  in set_qam128()
7555 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);  in set_qam128()
7556 	if (rc != 0) {  in set_qam128()
7557 		pr_err("error %d\n", rc);  in set_qam128()
7560 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);  in set_qam128()
7561 	if (rc != 0) {  in set_qam128()
7562 		pr_err("error %d\n", rc);  in set_qam128()
7565 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam128()
7566 	if (rc != 0) {  in set_qam128()
7567 		pr_err("error %d\n", rc);  in set_qam128()
7570 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam128()
7571 	if (rc != 0) {  in set_qam128()
7572 		pr_err("error %d\n", rc);  in set_qam128()
7575 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);  in set_qam128()
7576 	if (rc != 0) {  in set_qam128()
7577 		pr_err("error %d\n", rc);  in set_qam128()
7581 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);  in set_qam128()
7582 	if (rc != 0) {  in set_qam128()
7583 		pr_err("error %d\n", rc);  in set_qam128()
7589 	return rc;  in set_qam128()
7603 	int rc;  in set_qam256()  local
7621 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam256()
7622 	if (rc != 0) {  in set_qam256()
7623 		pr_err("error %d\n", rc);  in set_qam256()
7626 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam256()
7627 	if (rc != 0) {  in set_qam256()
7628 		pr_err("error %d\n", rc);  in set_qam256()
7632 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);  in set_qam256()
7633 	if (rc != 0) {  in set_qam256()
7634 		pr_err("error %d\n", rc);  in set_qam256()
7637 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);  in set_qam256()
7638 	if (rc != 0) {  in set_qam256()
7639 		pr_err("error %d\n", rc);  in set_qam256()
7642 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam256()
7643 	if (rc != 0) {  in set_qam256()
7644 		pr_err("error %d\n", rc);  in set_qam256()
7647 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);  in set_qam256()
7648 	if (rc != 0) {  in set_qam256()
7649 		pr_err("error %d\n", rc);  in set_qam256()
7652 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam256()
7653 	if (rc != 0) {  in set_qam256()
7654 		pr_err("error %d\n", rc);  in set_qam256()
7657 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);  in set_qam256()
7658 	if (rc != 0) {  in set_qam256()
7659 		pr_err("error %d\n", rc);  in set_qam256()
7663 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam256()
7664 	if (rc != 0) {  in set_qam256()
7665 		pr_err("error %d\n", rc);  in set_qam256()
7668 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);  in set_qam256()
7669 	if (rc != 0) {  in set_qam256()
7670 		pr_err("error %d\n", rc);  in set_qam256()
7673 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam256()
7674 	if (rc != 0) {  in set_qam256()
7675 		pr_err("error %d\n", rc);  in set_qam256()
7679 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);  in set_qam256()
7680 	if (rc != 0) {  in set_qam256()
7681 		pr_err("error %d\n", rc);  in set_qam256()
7684 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);  in set_qam256()
7685 	if (rc != 0) {  in set_qam256()
7686 		pr_err("error %d\n", rc);  in set_qam256()
7689 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);  in set_qam256()
7690 	if (rc != 0) {  in set_qam256()
7691 		pr_err("error %d\n", rc);  in set_qam256()
7694 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);  in set_qam256()
7695 	if (rc != 0) {  in set_qam256()
7696 		pr_err("error %d\n", rc);  in set_qam256()
7699 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);  in set_qam256()
7700 	if (rc != 0) {  in set_qam256()
7701 		pr_err("error %d\n", rc);  in set_qam256()
7704 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);  in set_qam256()
7705 	if (rc != 0) {  in set_qam256()
7706 		pr_err("error %d\n", rc);  in set_qam256()
7709 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);  in set_qam256()
7710 	if (rc != 0) {  in set_qam256()
7711 		pr_err("error %d\n", rc);  in set_qam256()
7715 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam256()
7716 	if (rc != 0) {  in set_qam256()
7717 		pr_err("error %d\n", rc);  in set_qam256()
7720 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam256()
7721 	if (rc != 0) {  in set_qam256()
7722 		pr_err("error %d\n", rc);  in set_qam256()
7725 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam256()
7726 	if (rc != 0) {  in set_qam256()
7727 		pr_err("error %d\n", rc);  in set_qam256()
7730 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);  in set_qam256()
7731 	if (rc != 0) {  in set_qam256()
7732 		pr_err("error %d\n", rc);  in set_qam256()
7735 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam256()
7736 	if (rc != 0) {  in set_qam256()
7737 		pr_err("error %d\n", rc);  in set_qam256()
7740 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam256()
7741 	if (rc != 0) {  in set_qam256()
7742 		pr_err("error %d\n", rc);  in set_qam256()
7745 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);  in set_qam256()
7746 	if (rc != 0) {  in set_qam256()
7747 		pr_err("error %d\n", rc);  in set_qam256()
7750 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);  in set_qam256()
7751 	if (rc != 0) {  in set_qam256()
7752 		pr_err("error %d\n", rc);  in set_qam256()
7755 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam256()
7756 	if (rc != 0) {  in set_qam256()
7757 		pr_err("error %d\n", rc);  in set_qam256()
7760 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam256()
7761 	if (rc != 0) {  in set_qam256()
7762 		pr_err("error %d\n", rc);  in set_qam256()
7765 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam256()
7766 	if (rc != 0) {  in set_qam256()
7767 		pr_err("error %d\n", rc);  in set_qam256()
7770 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam256()
7771 	if (rc != 0) {  in set_qam256()
7772 		pr_err("error %d\n", rc);  in set_qam256()
7775 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam256()
7776 	if (rc != 0) {  in set_qam256()
7777 		pr_err("error %d\n", rc);  in set_qam256()
7780 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam256()
7781 	if (rc != 0) {  in set_qam256()
7782 		pr_err("error %d\n", rc);  in set_qam256()
7785 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam256()
7786 	if (rc != 0) {  in set_qam256()
7787 		pr_err("error %d\n", rc);  in set_qam256()
7790 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);  in set_qam256()
7791 	if (rc != 0) {  in set_qam256()
7792 		pr_err("error %d\n", rc);  in set_qam256()
7795 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);  in set_qam256()
7796 	if (rc != 0) {  in set_qam256()
7797 		pr_err("error %d\n", rc);  in set_qam256()
7800 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam256()
7801 	if (rc != 0) {  in set_qam256()
7802 		pr_err("error %d\n", rc);  in set_qam256()
7805 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam256()
7806 	if (rc != 0) {  in set_qam256()
7807 		pr_err("error %d\n", rc);  in set_qam256()
7810 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);  in set_qam256()
7811 	if (rc != 0) {  in set_qam256()
7812 		pr_err("error %d\n", rc);  in set_qam256()
7816 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);  in set_qam256()
7817 	if (rc != 0) {  in set_qam256()
7818 		pr_err("error %d\n", rc);  in set_qam256()
7824 	return rc;  in set_qam256()
7846 	int rc;  in set_qam()  local
8050 		rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in set_qam()
8051 		if (rc != 0) {  in set_qam()
8052 			pr_err("error %d\n", rc);  in set_qam()
8055 		rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);  in set_qam()
8056 		if (rc != 0) {  in set_qam()
8057 			pr_err("error %d\n", rc);  in set_qam()
8060 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in set_qam()
8061 		if (rc != 0) {  in set_qam()
8062 			pr_err("error %d\n", rc);  in set_qam()
8065 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in set_qam()
8066 		if (rc != 0) {  in set_qam()
8067 			pr_err("error %d\n", rc);  in set_qam()
8070 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in set_qam()
8071 		if (rc != 0) {  in set_qam()
8072 			pr_err("error %d\n", rc);  in set_qam()
8075 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in set_qam()
8076 		if (rc != 0) {  in set_qam()
8077 			pr_err("error %d\n", rc);  in set_qam()
8080 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in set_qam()
8081 		if (rc != 0) {  in set_qam()
8082 			pr_err("error %d\n", rc);  in set_qam()
8092 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8093 		if (rc != 0) {  in set_qam()
8094 			pr_err("error %d\n", rc);  in set_qam()
8111 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8112 		if (rc != 0) {  in set_qam()
8113 			pr_err("error %d\n", rc);  in set_qam()
8123 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8124 		if (rc != 0) {  in set_qam()
8125 			pr_err("error %d\n", rc);  in set_qam()
8129 		rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);  in set_qam()
8130 		if (rc != 0) {  in set_qam()
8131 			pr_err("error %d\n", rc);  in set_qam()
8135 		rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);  in set_qam()
8136 		if (rc != 0) {  in set_qam()
8137 			pr_err("error %d\n", rc);  in set_qam()
8146 		rc = set_frequency(demod, channel, tuner_freq_offset);  in set_qam()
8147 		if (rc != 0) {  in set_qam()
8148 			pr_err("error %d\n", rc);  in set_qam()
8155 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);  in set_qam()
8156 		if (rc != 0) {  in set_qam()
8157 			pr_err("error %d\n", rc);  in set_qam()
8160 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);  in set_qam()
8161 		if (rc != 0) {  in set_qam()
8162 			pr_err("error %d\n", rc);  in set_qam()
8169 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);  in set_qam()
8170 			if (rc != 0) {  in set_qam()
8171 				pr_err("error %d\n", rc);  in set_qam()
8175 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);  in set_qam()
8176 		if (rc != 0) {  in set_qam()
8177 			pr_err("error %d\n", rc);  in set_qam()
8180 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);  in set_qam()
8181 		if (rc != 0) {  in set_qam()
8182 			pr_err("error %d\n", rc);  in set_qam()
8185 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);  in set_qam()
8186 		if (rc != 0) {  in set_qam()
8187 			pr_err("error %d\n", rc);  in set_qam()
8191 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);  in set_qam()
8192 		if (rc != 0) {  in set_qam()
8193 			pr_err("error %d\n", rc);  in set_qam()
8197 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);  in set_qam()
8198 		if (rc != 0) {  in set_qam()
8199 			pr_err("error %d\n", rc);  in set_qam()
8202 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);  in set_qam()
8203 		if (rc != 0) {  in set_qam()
8204 			pr_err("error %d\n", rc);  in set_qam()
8207 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);  in set_qam()
8208 		if (rc != 0) {  in set_qam()
8209 			pr_err("error %d\n", rc);  in set_qam()
8212 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);  in set_qam()
8213 		if (rc != 0) {  in set_qam()
8214 			pr_err("error %d\n", rc);  in set_qam()
8217 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);  in set_qam()
8218 		if (rc != 0) {  in set_qam()
8219 			pr_err("error %d\n", rc);  in set_qam()
8222 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);  in set_qam()
8223 		if (rc != 0) {  in set_qam()
8224 			pr_err("error %d\n", rc);  in set_qam()
8227 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);  in set_qam()
8228 		if (rc != 0) {  in set_qam()
8229 			pr_err("error %d\n", rc);  in set_qam()
8233 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);  in set_qam()
8234 		if (rc != 0) {  in set_qam()
8235 			pr_err("error %d\n", rc);  in set_qam()
8238 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);  in set_qam()
8239 		if (rc != 0) {  in set_qam()
8240 			pr_err("error %d\n", rc);  in set_qam()
8244 		rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);  in set_qam()
8245 		if (rc != 0) {  in set_qam()
8246 			pr_err("error %d\n", rc);  in set_qam()
8250 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);  in set_qam()
8251 			if (rc != 0) {  in set_qam()
8252 				pr_err("error %d\n", rc);  in set_qam()
8255 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);  in set_qam()
8256 			if (rc != 0) {  in set_qam()
8257 				pr_err("error %d\n", rc);  in set_qam()
8260 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);  in set_qam()
8261 			if (rc != 0) {  in set_qam()
8262 				pr_err("error %d\n", rc);  in set_qam()
8270 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);  in set_qam()
8271 				if (rc != 0) {  in set_qam()
8272 					pr_err("error %d\n", rc);  in set_qam()
8275 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);  in set_qam()
8276 				if (rc != 0) {  in set_qam()
8277 					pr_err("error %d\n", rc);  in set_qam()
8280 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);  in set_qam()
8281 				if (rc != 0) {  in set_qam()
8282 					pr_err("error %d\n", rc);  in set_qam()
8288 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);  in set_qam()
8289 				if (rc != 0) {  in set_qam()
8290 					pr_err("error %d\n", rc);  in set_qam()
8293 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);  in set_qam()
8294 				if (rc != 0) {  in set_qam()
8295 					pr_err("error %d\n", rc);  in set_qam()
8298 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);  in set_qam()
8299 				if (rc != 0) {  in set_qam()
8300 					pr_err("error %d\n", rc);  in set_qam()
8309 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);  in set_qam()
8310 		if (rc != 0) {  in set_qam()
8311 			pr_err("error %d\n", rc);  in set_qam()
8314 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);  in set_qam()
8315 		if (rc != 0) {  in set_qam()
8316 			pr_err("error %d\n", rc);  in set_qam()
8319 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);  in set_qam()
8320 		if (rc != 0) {  in set_qam()
8321 			pr_err("error %d\n", rc);  in set_qam()
8324 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);  in set_qam()
8325 		if (rc != 0) {  in set_qam()
8326 			pr_err("error %d\n", rc);  in set_qam()
8329 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);  in set_qam()
8330 		if (rc != 0) {  in set_qam()
8331 			pr_err("error %d\n", rc);  in set_qam()
8334 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);  in set_qam()
8335 		if (rc != 0) {  in set_qam()
8336 			pr_err("error %d\n", rc);  in set_qam()
8339 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);  in set_qam()
8340 		if (rc != 0) {  in set_qam()
8341 			pr_err("error %d\n", rc);  in set_qam()
8344 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);  in set_qam()
8345 		if (rc != 0) {  in set_qam()
8346 			pr_err("error %d\n", rc);  in set_qam()
8349 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);  in set_qam()
8350 		if (rc != 0) {  in set_qam()
8351 			pr_err("error %d\n", rc);  in set_qam()
8354 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);  in set_qam()
8355 		if (rc != 0) {  in set_qam()
8356 			pr_err("error %d\n", rc);  in set_qam()
8359 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);  in set_qam()
8360 		if (rc != 0) {  in set_qam()
8361 			pr_err("error %d\n", rc);  in set_qam()
8364 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);  in set_qam()
8365 		if (rc != 0) {  in set_qam()
8366 			pr_err("error %d\n", rc);  in set_qam()
8369 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);  in set_qam()
8370 		if (rc != 0) {  in set_qam()
8371 			pr_err("error %d\n", rc);  in set_qam()
8374 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);  in set_qam()
8375 		if (rc != 0) {  in set_qam()
8376 			pr_err("error %d\n", rc);  in set_qam()
8379 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);  in set_qam()
8380 		if (rc != 0) {  in set_qam()
8381 			pr_err("error %d\n", rc);  in set_qam()
8384 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);  in set_qam()
8385 		if (rc != 0) {  in set_qam()
8386 			pr_err("error %d\n", rc);  in set_qam()
8389 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);  in set_qam()
8390 		if (rc != 0) {  in set_qam()
8391 			pr_err("error %d\n", rc);  in set_qam()
8394 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);  in set_qam()
8395 		if (rc != 0) {  in set_qam()
8396 			pr_err("error %d\n", rc);  in set_qam()
8399 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);  in set_qam()
8400 		if (rc != 0) {  in set_qam()
8401 			pr_err("error %d\n", rc);  in set_qam()
8404 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);  in set_qam()
8405 		if (rc != 0) {  in set_qam()
8406 			pr_err("error %d\n", rc);  in set_qam()
8410 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);  in set_qam()
8411 		if (rc != 0) {  in set_qam()
8412 			pr_err("error %d\n", rc);  in set_qam()
8415 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);  in set_qam()
8416 		if (rc != 0) {  in set_qam()
8417 			pr_err("error %d\n", rc);  in set_qam()
8420 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);  in set_qam()
8421 		if (rc != 0) {  in set_qam()
8422 			pr_err("error %d\n", rc);  in set_qam()
8425 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);  in set_qam()
8426 		if (rc != 0) {  in set_qam()
8427 			pr_err("error %d\n", rc);  in set_qam()
8430 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);  in set_qam()
8431 		if (rc != 0) {  in set_qam()
8432 			pr_err("error %d\n", rc);  in set_qam()
8439 		rc = set_iqm_af(demod, true);  in set_qam()
8440 		if (rc != 0) {  in set_qam()
8441 			pr_err("error %d\n", rc);  in set_qam()
8444 		rc = adc_synchronization(demod);  in set_qam()
8445 		if (rc != 0) {  in set_qam()
8446 			pr_err("error %d\n", rc);  in set_qam()
8450 		rc = init_agc(demod);  in set_qam()
8451 		if (rc != 0) {  in set_qam()
8452 			pr_err("error %d\n", rc);  in set_qam()
8455 		rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);  in set_qam()
8456 		if (rc != 0) {  in set_qam()
8457 			pr_err("error %d\n", rc);  in set_qam()
8460 		rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);  in set_qam()
8461 		if (rc != 0) {  in set_qam()
8462 			pr_err("error %d\n", rc);  in set_qam()
8471 			rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);  in set_qam()
8472 			if (rc != 0) {  in set_qam()
8473 				pr_err("error %d\n", rc);  in set_qam()
8477 		rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));  in set_qam()
8478 		if (rc != 0) {  in set_qam()
8479 			pr_err("error %d\n", rc);  in set_qam()
8486 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), …  in set_qam()
8487 			if (rc != 0) {  in set_qam()
8488 				pr_err("error %d\n", rc);  in set_qam()
8491 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), …  in set_qam()
8492 			if (rc != 0) {  in set_qam()
8493 				pr_err("error %d\n", rc);  in set_qam()
8499 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap…  in set_qam()
8500 				if (rc != 0) {  in set_qam()
8501 					pr_err("error %d\n", rc);  in set_qam()
8504 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap…  in set_qam()
8505 				if (rc != 0) {  in set_qam()
8506 					pr_err("error %d\n", rc);  in set_qam()
8511 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t…  in set_qam()
8512 				if (rc != 0) {  in set_qam()
8513 					pr_err("error %d\n", rc);  in set_qam()
8516 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t…  in set_qam()
8517 				if (rc != 0) {  in set_qam()
8518 					pr_err("error %d\n", rc);  in set_qam()
8526 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), …  in set_qam()
8527 			if (rc != 0) {  in set_qam()
8528 				pr_err("error %d\n", rc);  in set_qam()
8531 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), …  in set_qam()
8532 			if (rc != 0) {  in set_qam()
8533 				pr_err("error %d\n", rc);  in set_qam()
8541 			rc = set_qam16(demod);  in set_qam()
8542 			if (rc != 0) {  in set_qam()
8543 				pr_err("error %d\n", rc);  in set_qam()
8548 			rc = set_qam32(demod);  in set_qam()
8549 			if (rc != 0) {  in set_qam()
8550 				pr_err("error %d\n", rc);  in set_qam()
8555 			rc = set_qam64(demod);  in set_qam()
8556 			if (rc != 0) {  in set_qam()
8557 				pr_err("error %d\n", rc);  in set_qam()
8562 			rc = set_qam128(demod);  in set_qam()
8563 			if (rc != 0) {  in set_qam()
8564 				pr_err("error %d\n", rc);  in set_qam()
8569 			rc = set_qam256(demod);  in set_qam()
8570 			if (rc != 0) {  in set_qam()
8571 				pr_err("error %d\n", rc);  in set_qam()
8581 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);  in set_qam()
8582 		if (rc != 0) {  in set_qam()
8583 			pr_err("error %d\n", rc);  in set_qam()
8588 		rc = set_mpegtei_handling(demod);  in set_qam()
8589 		if (rc != 0) {  in set_qam()
8590 			pr_err("error %d\n", rc);  in set_qam()
8593 		rc = bit_reverse_mpeg_output(demod);  in set_qam()
8594 		if (rc != 0) {  in set_qam()
8595 			pr_err("error %d\n", rc);  in set_qam()
8598 		rc = set_mpeg_start_width(demod);  in set_qam()
8599 		if (rc != 0) {  in set_qam()
8600 			pr_err("error %d\n", rc);  in set_qam()
8611 			rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in set_qam()
8612 			if (rc != 0) {  in set_qam()
8613 				pr_err("error %d\n", rc);  in set_qam()
8628 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8629 		if (rc != 0) {  in set_qam()
8630 			pr_err("error %d\n", rc);  in set_qam()
8635 	rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);  in set_qam()
8636 	if (rc != 0) {  in set_qam()
8637 		pr_err("error %d\n", rc);  in set_qam()
8640 	rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);  in set_qam()
8641 	if (rc != 0) {  in set_qam()
8642 		pr_err("error %d\n", rc);  in set_qam()
8645 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);  in set_qam()
8646 	if (rc != 0) {  in set_qam()
8647 		pr_err("error %d\n", rc);  in set_qam()
8653 	return rc;  in set_qam()
8663 	int rc;  in qam_flip_spec()  local
8674 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);  in qam_flip_spec()
8675 	if (rc != 0) {  in qam_flip_spec()
8676 		pr_err("error %d\n", rc);  in qam_flip_spec()
8679 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_AC…  in qam_flip_spec()
8680 	if (rc != 0) {  in qam_flip_spec()
8681 		pr_err("error %d\n", rc);  in qam_flip_spec()
8686 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);  in qam_flip_spec()
8687 	if (rc != 0) {  in qam_flip_spec()
8688 		pr_err("error %d\n", rc);  in qam_flip_spec()
8691 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);  in qam_flip_spec()
8692 	if (rc != 0) {  in qam_flip_spec()
8693 		pr_err("error %d\n", rc);  in qam_flip_spec()
8697 	rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);  in qam_flip_spec()
8698 	if (rc != 0) {  in qam_flip_spec()
8699 		pr_err("error %d\n", rc);  in qam_flip_spec()
8702 	rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);  in qam_flip_spec()
8703 	if (rc != 0) {  in qam_flip_spec()
8704 		pr_err("error %d\n", rc);  in qam_flip_spec()
8712 	rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);  in qam_flip_spec()
8713 	if (rc != 0) {  in qam_flip_spec()
8714 		pr_err("error %d\n", rc);  in qam_flip_spec()
8718 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);  in qam_flip_spec()
8719 	if (rc != 0) {  in qam_flip_spec()
8720 		pr_err("error %d\n", rc);  in qam_flip_spec()
8723 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);  in qam_flip_spec()
8724 	if (rc != 0) {  in qam_flip_spec()
8725 		pr_err("error %d\n", rc);  in qam_flip_spec()
8730 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);  in qam_flip_spec()
8731 	if (rc != 0) {  in qam_flip_spec()
8732 		pr_err("error %d\n", rc);  in qam_flip_spec()
8735 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);  in qam_flip_spec()
8736 	if (rc != 0) {  in qam_flip_spec()
8737 		pr_err("error %d\n", rc);  in qam_flip_spec()
8740 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);  in qam_flip_spec()
8741 	if (rc != 0) {  in qam_flip_spec()
8742 		pr_err("error %d\n", rc);  in qam_flip_spec()
8747 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);  in qam_flip_spec()
8748 	if (rc != 0) {  in qam_flip_spec()
8749 		pr_err("error %d\n", rc);  in qam_flip_spec()
8756 	rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);  in qam_flip_spec()
8757 	if (rc != 0) {  in qam_flip_spec()
8758 		pr_err("error %d\n", rc);  in qam_flip_spec()
8763 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);  in qam_flip_spec()
8764 	if (rc != 0) {  in qam_flip_spec()
8765 		pr_err("error %d\n", rc);  in qam_flip_spec()
8768 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);  in qam_flip_spec()
8769 	if (rc != 0) {  in qam_flip_spec()
8770 		pr_err("error %d\n", rc);  in qam_flip_spec()
8775 		rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);  in qam_flip_spec()
8776 		if (rc != 0) {  in qam_flip_spec()
8777 			pr_err("error %d\n", rc);  in qam_flip_spec()
8780 		rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);  in qam_flip_spec()
8781 		if (rc != 0) {  in qam_flip_spec()
8782 			pr_err("error %d\n", rc);  in qam_flip_spec()
8788 		rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);  in qam_flip_spec()
8789 		if (rc != 0) {  in qam_flip_spec()
8790 			pr_err("error %d\n", rc);  in qam_flip_spec()
8793 		rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);  in qam_flip_spec()
8794 		if (rc != 0) {  in qam_flip_spec()
8795 			pr_err("error %d\n", rc);  in qam_flip_spec()
8801 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);  in qam_flip_spec()
8802 	if (rc != 0) {  in qam_flip_spec()
8803 		pr_err("error %d\n", rc);  in qam_flip_spec()
8806 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);  in qam_flip_spec()
8807 	if (rc != 0) {  in qam_flip_spec()
8808 		pr_err("error %d\n", rc);  in qam_flip_spec()
8812 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);  in qam_flip_spec()
8813 	if (rc != 0) {  in qam_flip_spec()
8814 		pr_err("error %d\n", rc);  in qam_flip_spec()
8820 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);  in qam_flip_spec()
8821 		if (rc != 0) {  in qam_flip_spec()
8822 			pr_err("error %d\n", rc);  in qam_flip_spec()
8826 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);  in qam_flip_spec()
8827 	if (rc != 0) {  in qam_flip_spec()
8828 		pr_err("error %d\n", rc);  in qam_flip_spec()
8834 	return rc;  in qam_flip_spec()
8860 	int rc;  in qam64auto()  local
8872 		rc = ctrl_lock_status(demod, lock_status);  in qam64auto()
8873 		if (rc != 0) {  in qam64auto()
8874 			pr_err("error %d\n", rc);  in qam64auto()
8881 				rc = ctrl_get_qam_sig_quality(demod);  in qam64auto()
8882 				if (rc != 0) {  in qam64auto()
8883 					pr_err("error %d\n", rc);  in qam64auto()
8898 				rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);  in qam64auto()
8899 				if (rc != 0) {  in qam64auto()
8900 					pr_err("error %d\n", rc);  in qam64auto()
8903 				rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);  in qam64auto()
8904 				if (rc != 0) {  in qam64auto()
8905 					pr_err("error %d\n", rc);  in qam64auto()
8916 					rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);  in qam64auto()
8917 					if (rc != 0) {  in qam64auto()
8918 						pr_err("error %d\n", rc);  in qam64auto()
8921 					rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);  in qam64auto()
8922 					if (rc != 0) {  in qam64auto()
8923 						pr_err("error %d\n", rc);  in qam64auto()
8928 					rc = qam_flip_spec(demod, channel);  in qam64auto()
8929 					if (rc != 0) {  in qam64auto()
8930 						pr_err("error %d\n", rc);  in qam64auto()
8950 				rc = ctrl_get_qam_sig_quality(demod);  in qam64auto()
8951 				if (rc != 0) {  in qam64auto()
8952 					pr_err("error %d\n", rc);  in qam64auto()
8956 					rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);  in qam64auto()
8957 					if (rc != 0) {  in qam64auto()
8958 						pr_err("error %d\n", rc);  in qam64auto()
8961 					rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);  in qam64auto()
8962 					if (rc != 0) {  in qam64auto()
8963 						pr_err("error %d\n", rc);  in qam64auto()
8987 	return rc;  in qam64auto()
9008 	int rc;  in qam256auto()  local
9019 		rc = ctrl_lock_status(demod, lock_status);  in qam256auto()
9020 		if (rc != 0) {  in qam256auto()
9021 			pr_err("error %d\n", rc);  in qam256auto()
9027 				rc = ctrl_get_qam_sig_quality(demod);  in qam256auto()
9028 				if (rc != 0) {  in qam256auto()
9029 					pr_err("error %d\n", rc);  in qam256auto()
9045 					rc = qam_flip_spec(demod, channel);  in qam256auto()
9046 					if (rc != 0) {  in qam256auto()
9047 						pr_err("error %d\n", rc);  in qam256auto()
9071 	return rc;  in qam256auto()
9086 	int rc;  in set_qam_channel()  local
9110 		rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);  in set_qam_channel()
9111 		if (rc != 0) {  in set_qam_channel()
9112 			pr_err("error %d\n", rc);  in set_qam_channel()
9117 			rc = qam64auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9120 			rc = qam256auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9122 		if (rc != 0) {  in set_qam_channel()
9123 			pr_err("error %d\n", rc);  in set_qam_channel()
9140 			rc = set_qam(demod, channel, tuner_freq_offset,  in set_qam_channel()
9142 			if (rc != 0) {  in set_qam_channel()
9143 				pr_err("error %d\n", rc);  in set_qam_channel()
9146 			rc = qam256auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9148 			if (rc != 0) {  in set_qam_channel()
9149 				pr_err("error %d\n", rc);  in set_qam_channel()
9166 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9169 			if (rc != 0) {  in set_qam_channel()
9170 				pr_err("error %d\n", rc);  in set_qam_channel()
9173 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9176 			if (rc != 0) {  in set_qam_channel()
9177 				pr_err("error %d\n", rc);  in set_qam_channel()
9180 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9183 			if (rc != 0) {  in set_qam_channel()
9184 				pr_err("error %d\n", rc);  in set_qam_channel()
9188 			rc = set_qam(demod, channel, tuner_freq_offset,  in set_qam_channel()
9190 			if (rc != 0) {  in set_qam_channel()
9191 				pr_err("error %d\n", rc);  in set_qam_channel()
9194 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9197 			if (rc != 0) {  in set_qam_channel()
9198 				pr_err("error %d\n", rc);  in set_qam_channel()
9202 			rc = qam64auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9204 			if (rc != 0) {  in set_qam_channel()
9205 				pr_err("error %d\n", rc);  in set_qam_channel()
9221 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9224 			if (rc != 0) {  in set_qam_channel()
9225 				pr_err("error %d\n", rc);  in set_qam_channel()
9228 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9231 			if (rc != 0) {  in set_qam_channel()
9232 				pr_err("error %d\n", rc);  in set_qam_channel()
9235 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9238 			if (rc != 0) {  in set_qam_channel()
9239 				pr_err("error %d\n", rc);  in set_qam_channel()
9243 			rc = set_qam(demod, channel, tuner_freq_offset,  in set_qam_channel()
9245 			if (rc != 0) {  in set_qam_channel()
9246 				pr_err("error %d\n", rc);  in set_qam_channel()
9249 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9252 			if (rc != 0) {  in set_qam_channel()
9253 				pr_err("error %d\n", rc);  in set_qam_channel()
9256 			rc = qam64auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9258 			if (rc != 0) {  in set_qam_channel()
9259 				pr_err("error %d\n", rc);  in set_qam_channel()
9276 	return rc;  in set_qam_channel()
9293 	int rc;  in get_qamrs_err_count()  local
9305 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);  in get_qamrs_err_count()
9306 	if (rc != 0) {  in get_qamrs_err_count()
9307 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9311 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);  in get_qamrs_err_count()
9312 	if (rc != 0) {  in get_qamrs_err_count()
9313 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9317 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);  in get_qamrs_err_count()
9318 	if (rc != 0) {  in get_qamrs_err_count()
9319 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9323 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);  in get_qamrs_err_count()
9324 	if (rc != 0) {  in get_qamrs_err_count()
9325 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9329 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);  in get_qamrs_err_count()
9330 	if (rc != 0) {  in get_qamrs_err_count()
9331 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9347 	return rc;  in get_qamrs_err_count()
9370 	int rc;  in get_sig_strength()  local
9378 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);  in get_sig_strength()
9379 	if (rc != 0) {  in get_sig_strength()
9380 		pr_err("error %d\n", rc);  in get_sig_strength()
9384 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);  in get_sig_strength()
9385 	if (rc != 0) {  in get_sig_strength()
9386 		pr_err("error %d\n", rc);  in get_sig_strength()
9429 	return rc;  in get_sig_strength()
9453 	int rc;  in ctrl_get_qam_sig_quality()  local
9483 	rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);  in ctrl_get_qam_sig_quality()
9484 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9485 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9489 	rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);  in ctrl_get_qam_sig_quality()
9490 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9491 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9495 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);  in ctrl_get_qam_sig_quality()
9496 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9497 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9548 	rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);  in ctrl_get_qam_sig_quality()
9549 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9550 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9630 	rc = get_acc_pkt_err(demod, &sig_quality->packet_error);  in ctrl_get_qam_sig_quality()
9631 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9632 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9646 	return rc;  in ctrl_get_qam_sig_quality()
9738 	int rc;  in power_down_atv()  local
9750 	rc = scu_command(dev_addr, &cmd_scu);  in power_down_atv()
9751 	if (rc != 0) {  in power_down_atv()
9752 		pr_err("error %d\n", rc);  in power_down_atv()
9756 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP…  in power_down_atv()
9757 	if (rc != 0) {  in power_down_atv()
9758 		pr_err("error %d\n", rc);  in power_down_atv()
9762 	rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);  in power_down_atv()
9763 	if (rc != 0) {  in power_down_atv()
9764 		pr_err("error %d\n", rc);  in power_down_atv()
9768 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);  in power_down_atv()
9769 		if (rc != 0) {  in power_down_atv()
9770 			pr_err("error %d\n", rc);  in power_down_atv()
9773 		rc = set_iqm_af(demod, false);  in power_down_atv()
9774 		if (rc != 0) {  in power_down_atv()
9775 			pr_err("error %d\n", rc);  in power_down_atv()
9779 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in power_down_atv()
9780 		if (rc != 0) {  in power_down_atv()
9781 			pr_err("error %d\n", rc);  in power_down_atv()
9784 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in power_down_atv()
9785 		if (rc != 0) {  in power_down_atv()
9786 			pr_err("error %d\n", rc);  in power_down_atv()
9789 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in power_down_atv()
9790 		if (rc != 0) {  in power_down_atv()
9791 			pr_err("error %d\n", rc);  in power_down_atv()
9794 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in power_down_atv()
9795 		if (rc != 0) {  in power_down_atv()
9796 			pr_err("error %d\n", rc);  in power_down_atv()
9799 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in power_down_atv()
9800 		if (rc != 0) {  in power_down_atv()
9801 			pr_err("error %d\n", rc);  in power_down_atv()
9805 	rc = power_down_aud(demod);  in power_down_atv()
9806 	if (rc != 0) {  in power_down_atv()
9807 		pr_err("error %d\n", rc);  in power_down_atv()
9813 	return rc;  in power_down_atv()
9828 	int rc;  in power_down_aud()  local
9833 	rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);  in power_down_aud()
9834 	if (rc != 0) {  in power_down_aud()
9835 		pr_err("error %d\n", rc);  in power_down_aud()
9843 	return rc;  in power_down_aud()
9856 	int rc;  in set_orx_nsu_aox()  local
9860 	rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);  in set_orx_nsu_aox()
9861 	if (rc != 0) {  in set_orx_nsu_aox()
9862 		pr_err("error %d\n", rc);  in set_orx_nsu_aox()
9869 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);  in set_orx_nsu_aox()
9870 	if (rc != 0) {  in set_orx_nsu_aox()
9871 		pr_err("error %d\n", rc);  in set_orx_nsu_aox()
9877 	return rc;  in set_orx_nsu_aox()
9906 	int rc;  in ctrl_set_oob()  local
9943 		rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
9944 		if (rc != 0) {  in ctrl_set_oob()
9945 			pr_err("error %d\n", rc);  in ctrl_set_oob()
9948 		rc = set_orx_nsu_aox(demod, false);  in ctrl_set_oob()
9949 		if (rc != 0) {  in ctrl_set_oob()
9950 			pr_err("error %d\n", rc);  in ctrl_set_oob()
9953 		rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);  in ctrl_set_oob()
9954 		if (rc != 0) {  in ctrl_set_oob()
9955 			pr_err("error %d\n", rc);  in ctrl_set_oob()
9985 	rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);  in ctrl_set_oob()
9986 	if (rc != 0) {  in ctrl_set_oob()
9987 		pr_err("error %d\n", rc);  in ctrl_set_oob()
9995 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
9996 	if (rc != 0) {  in ctrl_set_oob()
9997 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10008 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
10009 	if (rc != 0) {  in ctrl_set_oob()
10010 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10084 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
10085 	if (rc != 0) {  in ctrl_set_oob()
10086 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10090 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);  in ctrl_set_oob()
10091 	if (rc != 0) {  in ctrl_set_oob()
10092 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10095 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_…  in ctrl_set_oob()
10096 	if (rc != 0) {  in ctrl_set_oob()
10097 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10100 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_…  in ctrl_set_oob()
10101 	if (rc != 0) {  in ctrl_set_oob()
10102 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10105 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_oob()
10106 	if (rc != 0) {  in ctrl_set_oob()
10107 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10111 	rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);  in ctrl_set_oob()
10112 	if (rc != 0) {  in ctrl_set_oob()
10113 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10116 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);  in ctrl_set_oob()
10117 	if (rc != 0) {  in ctrl_set_oob()
10118 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10121 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);  in ctrl_set_oob()
10122 	if (rc != 0) {  in ctrl_set_oob()
10123 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10128 	rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);  in ctrl_set_oob()
10129 	if (rc != 0) {  in ctrl_set_oob()
10130 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10135 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);  in ctrl_set_oob()
10136 	if (rc != 0) {  in ctrl_set_oob()
10137 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10142 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_S…  in ctrl_set_oob()
10143 	if (rc != 0) {  in ctrl_set_oob()
10144 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10147 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048…  in ctrl_set_oob()
10148 	if (rc != 0) {  in ctrl_set_oob()
10149 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10154 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);  in ctrl_set_oob()
10155 	if (rc != 0) {  in ctrl_set_oob()
10156 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10159 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);  in ctrl_set_oob()
10160 	if (rc != 0) {  in ctrl_set_oob()
10161 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10164 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);  in ctrl_set_oob()
10165 	if (rc != 0) {  in ctrl_set_oob()
10166 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10169 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);  in ctrl_set_oob()
10170 	if (rc != 0) {  in ctrl_set_oob()
10171 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10176 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);  in ctrl_set_oob()
10177 	if (rc != 0) {  in ctrl_set_oob()
10178 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10181 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10182 	if (rc != 0) {  in ctrl_set_oob()
10183 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10186 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10187 	if (rc != 0) {  in ctrl_set_oob()
10188 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10191 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10192 	if (rc != 0) {  in ctrl_set_oob()
10193 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10196 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);  in ctrl_set_oob()
10197 	if (rc != 0) {  in ctrl_set_oob()
10198 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10203 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);  in ctrl_set_oob()
10204 	if (rc != 0) {  in ctrl_set_oob()
10205 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10208 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10209 	if (rc != 0) {  in ctrl_set_oob()
10210 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10213 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10214 	if (rc != 0) {  in ctrl_set_oob()
10215 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10218 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10219 	if (rc != 0) {  in ctrl_set_oob()
10220 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10223 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);  in ctrl_set_oob()
10224 	if (rc != 0) {  in ctrl_set_oob()
10225 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10230 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);  in ctrl_set_oob()
10231 	if (rc != 0) {  in ctrl_set_oob()
10232 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10235 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10236 	if (rc != 0) {  in ctrl_set_oob()
10237 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10240 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10241 	if (rc != 0) {  in ctrl_set_oob()
10242 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10245 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10246 	if (rc != 0) {  in ctrl_set_oob()
10247 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10250 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);  in ctrl_set_oob()
10251 	if (rc != 0) {  in ctrl_set_oob()
10252 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10257 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);  in ctrl_set_oob()
10258 	if (rc != 0) {  in ctrl_set_oob()
10259 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10262 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10263 	if (rc != 0) {  in ctrl_set_oob()
10264 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10267 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10268 	if (rc != 0) {  in ctrl_set_oob()
10269 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10272 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10273 	if (rc != 0) {  in ctrl_set_oob()
10274 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10277 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);  in ctrl_set_oob()
10278 	if (rc != 0) {  in ctrl_set_oob()
10279 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10284 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);  in ctrl_set_oob()
10285 	if (rc != 0) {  in ctrl_set_oob()
10286 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10289 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10290 	if (rc != 0) {  in ctrl_set_oob()
10291 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10294 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10295 	if (rc != 0) {  in ctrl_set_oob()
10296 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10299 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10300 	if (rc != 0) {  in ctrl_set_oob()
10301 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10304 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);  in ctrl_set_oob()
10305 	if (rc != 0) {  in ctrl_set_oob()
10306 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10311 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);  in ctrl_set_oob()
10312 	if (rc != 0) {  in ctrl_set_oob()
10313 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10316 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10317 	if (rc != 0) {  in ctrl_set_oob()
10318 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10321 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);  in ctrl_set_oob()
10322 	if (rc != 0) {  in ctrl_set_oob()
10323 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10326 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);  in ctrl_set_oob()
10327 	if (rc != 0) {  in ctrl_set_oob()
10328 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10331 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);  in ctrl_set_oob()
10332 	if (rc != 0) {  in ctrl_set_oob()
10333 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10338 …rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)…  in ctrl_set_oob()
10339 	if (rc != 0) {  in ctrl_set_oob()
10340 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10343 	rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);  in ctrl_set_oob()
10344 	if (rc != 0) {  in ctrl_set_oob()
10345 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10351 		rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);  in ctrl_set_oob()
10352 		if (rc != 0) {  in ctrl_set_oob()
10353 			pr_err("error %d\n", rc);  in ctrl_set_oob()
10356 		rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);  in ctrl_set_oob()
10357 		if (rc != 0) {  in ctrl_set_oob()
10358 			pr_err("error %d\n", rc);  in ctrl_set_oob()
10362 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);  in ctrl_set_oob()
10363 	if (rc != 0) {  in ctrl_set_oob()
10364 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10367 	rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);  in ctrl_set_oob()
10368 	if (rc != 0) {  in ctrl_set_oob()
10369 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10380 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
10381 	if (rc != 0) {  in ctrl_set_oob()
10382 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10386 	rc = set_orx_nsu_aox(demod, true);  in ctrl_set_oob()
10387 	if (rc != 0) {  in ctrl_set_oob()
10388 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10391 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);  in ctrl_set_oob()
10392 	if (rc != 0) {  in ctrl_set_oob()
10393 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10401 	return rc;  in ctrl_set_oob()
10429 	int rc;  in ctrl_set_channel()  local
10492 		rc = ctrl_set_uio_cfg(demod, &uio_cfg);  in ctrl_set_channel()
10493 		if (rc != 0) {  in ctrl_set_channel()
10494 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10587 		rc = ctrl_uio_write(demod, &uio1);  in ctrl_set_channel()
10588 		if (rc != 0) {  in ctrl_set_channel()
10589 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10594 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);  in ctrl_set_channel()
10595 	if (rc != 0) {  in ctrl_set_channel()
10596 		pr_err("error %d\n", rc);  in ctrl_set_channel()
10609 		rc = set_vsb(demod);  in ctrl_set_channel()
10610 		if (rc != 0) {  in ctrl_set_channel()
10611 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10614 		rc = set_frequency(demod, channel, tuner_freq_offset);  in ctrl_set_channel()
10615 		if (rc != 0) {  in ctrl_set_channel()
10616 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10624 		rc = set_qam_channel(demod, channel, tuner_freq_offset);  in ctrl_set_channel()
10625 		if (rc != 0) {  in ctrl_set_channel()
10626 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10641 	return rc;  in ctrl_set_channel()
10668 	int rc;  in ctrl_sig_quality()  local
10672 	rc = get_sig_strength(demod, &strength);  in ctrl_sig_quality()
10673 	if (rc < 0) {  in ctrl_sig_quality()
10674 		pr_err("error getting signal strength %d\n", rc);  in ctrl_sig_quality()
10684 		rc = get_acc_pkt_err(demod, &pkt);  in ctrl_sig_quality()
10685 		if (rc != 0) {  in ctrl_sig_quality()
10686 			pr_err("error %d\n", rc);  in ctrl_sig_quality()
10699 			rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);  in ctrl_sig_quality()
10700 			if (rc != 0) {  in ctrl_sig_quality()
10701 				pr_err("error %d getting UCB\n", rc);  in ctrl_sig_quality()
10711 			rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);  in ctrl_sig_quality()
10712 			if (rc != 0) {  in ctrl_sig_quality()
10713 				pr_err("error %d getting pre-ber\n", rc);  in ctrl_sig_quality()
10722 			rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);  in ctrl_sig_quality()
10723 			if (rc != 0) {  in ctrl_sig_quality()
10724 				pr_err("error %d getting post-ber\n", rc);  in ctrl_sig_quality()
10732 			rc = get_vsbmer(dev_addr, &mer);  in ctrl_sig_quality()
10733 			if (rc != 0) {  in ctrl_sig_quality()
10734 				pr_err("error %d getting MER\n", rc);  in ctrl_sig_quality()
10746 		rc = ctrl_get_qam_sig_quality(demod);  in ctrl_sig_quality()
10747 		if (rc != 0) {  in ctrl_sig_quality()
10748 			pr_err("error %d\n", rc);  in ctrl_sig_quality()
10759 	return rc;  in ctrl_sig_quality()
10784 	int rc;  in ctrl_lock_status()  local
10823 	rc = scu_command(dev_addr, &cmd_scu);  in ctrl_lock_status()
10824 	if (rc != 0) {  in ctrl_lock_status()
10825 		pr_err("error %d\n", rc);  in ctrl_lock_status()
10847 	return rc;  in ctrl_lock_status()
10866 	int rc;  in ctrl_set_standard()  local
10884 		rc = power_down_qam(demod, false);  in ctrl_set_standard()
10885 		if (rc != 0) {  in ctrl_set_standard()
10886 			pr_err("error %d\n", rc);  in ctrl_set_standard()
10892 		rc = power_down_vsb(demod, false);  in ctrl_set_standard()
10893 		if (rc != 0) {  in ctrl_set_standard()
10894 			pr_err("error %d\n", rc);  in ctrl_set_standard()
10919 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);  in ctrl_set_standard()
10920 			if (rc != 0) {  in ctrl_set_standard()
10921 				pr_err("error %d\n", rc);  in ctrl_set_standard()
10928 		rc = set_vsb_leak_n_gain(demod);  in ctrl_set_standard()
10929 		if (rc != 0) {  in ctrl_set_standard()
10930 			pr_err("error %d\n", rc);  in ctrl_set_standard()
10944 	return rc;  in ctrl_set_standard()
11026 	int rc;  in ctrl_power_mode()  local
11063 		rc = power_up_device(demod);  in ctrl_power_mode()
11064 		if (rc != 0) {  in ctrl_power_mode()
11065 			pr_err("error %d\n", rc);  in ctrl_power_mode()
11091 			rc = power_down_qam(demod, true);  in ctrl_power_mode()
11092 			if (rc != 0) {  in ctrl_power_mode()
11093 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11098 			rc = power_down_vsb(demod, true);  in ctrl_power_mode()
11099 			if (rc != 0) {  in ctrl_power_mode()
11100 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11111 			rc = power_down_atv(demod, ext_attr->standard, true);  in ctrl_power_mode()
11112 			if (rc != 0) {  in ctrl_power_mode()
11113 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11128 		rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);  in ctrl_power_mode()
11129 		if (rc != 0) {  in ctrl_power_mode()
11130 			pr_err("error %d\n", rc);  in ctrl_power_mode()
11133 		rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);  in ctrl_power_mode()
11134 		if (rc != 0) {  in ctrl_power_mode()
11135 			pr_err("error %d\n", rc);  in ctrl_power_mode()
11141 			rc = init_hi(demod);  in ctrl_power_mode()
11142 			if (rc != 0) {  in ctrl_power_mode()
11143 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11148 			rc = hi_cfg_command(demod);  in ctrl_power_mode()
11149 			if (rc != 0) {  in ctrl_power_mode()
11150 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11160 	return rc;  in ctrl_power_mode()
11183 	int rc;  in ctrl_set_cfg_pre_saw()  local
11200 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);  in ctrl_set_cfg_pre_saw()
11201 		if (rc != 0) {  in ctrl_set_cfg_pre_saw()
11202 			pr_err("error %d\n", rc);  in ctrl_set_cfg_pre_saw()
11225 	return rc;  in ctrl_set_cfg_pre_saw()
11246 	int rc;  in ctrl_set_cfg_afe_gain()  local
11281 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);  in ctrl_set_cfg_afe_gain()
11282 			if (rc != 0) {  in ctrl_set_cfg_afe_gain()
11283 				pr_err("error %d\n", rc);  in ctrl_set_cfg_afe_gain()
11306 	return rc;  in ctrl_set_cfg_afe_gain()
11339 	int rc;  in drxj_open()  local
11358 	rc = ctrl_power_mode(demod, &power_mode);  in drxj_open()
11359 	if (rc != 0) {  in drxj_open()
11360 		pr_err("error %d\n", rc);  in drxj_open()
11364 		rc = -EINVAL;  in drxj_open()
11370 	rc = get_device_capabilities(demod);  in drxj_open()
11371 	if (rc != 0) {  in drxj_open()
11372 		pr_err("error %d\n", rc);  in drxj_open()
11384 …rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SO…  in drxj_open()
11385 	if (rc != 0) {  in drxj_open()
11386 		pr_err("error %d\n", rc);  in drxj_open()
11389 	rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);  in drxj_open()
11390 	if (rc != 0) {  in drxj_open()
11391 		pr_err("error %d\n", rc);  in drxj_open()
11398 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_…  in drxj_open()
11399 	if (rc != 0) {  in drxj_open()
11400 		pr_err("error %d\n", rc);  in drxj_open()
11404 	rc = set_iqm_af(demod, false);  in drxj_open()
11405 	if (rc != 0) {  in drxj_open()
11406 		pr_err("error %d\n", rc);  in drxj_open()
11409 	rc = set_orx_nsu_aox(demod, false);  in drxj_open()
11410 	if (rc != 0) {  in drxj_open()
11411 		pr_err("error %d\n", rc);  in drxj_open()
11415 	rc = init_hi(demod);  in drxj_open()
11416 	if (rc != 0) {  in drxj_open()
11417 		pr_err("error %d\n", rc);  in drxj_open()
11425 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in drxj_open()
11426 	if (rc != 0) {  in drxj_open()
11427 		pr_err("error %d\n", rc);  in drxj_open()
11431 	rc = power_down_aud(demod);  in drxj_open()
11432 	if (rc != 0) {  in drxj_open()
11433 		pr_err("error %d\n", rc);  in drxj_open()
11437 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);  in drxj_open()
11438 	if (rc != 0) {  in drxj_open()
11439 		pr_err("error %d\n", rc);  in drxj_open()
11455 		rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);  in drxj_open()
11456 		if (rc != 0) {  in drxj_open()
11457 			pr_err("error %d while uploading the firmware\n", rc);  in drxj_open()
11461 			rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);  in drxj_open()
11462 			if (rc != 0) {  in drxj_open()
11464 				       rc);  in drxj_open()
11472 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);  in drxj_open()
11473 	if (rc != 0) {  in drxj_open()
11474 		pr_err("error %d\n", rc);  in drxj_open()
11485 	rc = smart_ant_init(demod);  in drxj_open()
11486 	if (rc != 0) {  in drxj_open()
11487 		pr_err("error %d\n", rc);  in drxj_open()
11510 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);  in drxj_open()
11511 	if (rc != 0) {  in drxj_open()
11512 		pr_err("error %d\n", rc);  in drxj_open()
11515 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);  in drxj_open()
11516 	if (rc != 0) {  in drxj_open()
11517 		pr_err("error %d\n", rc);  in drxj_open()
11521 	rc = ctrl_set_oob(demod, NULL);  in drxj_open()
11522 	if (rc != 0) {  in drxj_open()
11523 		pr_err("error %d\n", rc);  in drxj_open()
11535 	return rc;  in drxj_open()
11548 	int rc;  in drxj_close()  local
11559 	rc = ctrl_power_mode(demod, &power_mode);  in drxj_close()
11560 	if (rc != 0) {  in drxj_close()
11561 		pr_err("error %d\n", rc);  in drxj_close()
11565 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);  in drxj_close()
11566 	if (rc != 0) {  in drxj_close()
11567 		pr_err("error %d\n", rc);  in drxj_close()
11571 	rc = ctrl_power_mode(demod, &power_mode);  in drxj_close()
11572 	if (rc != 0) {  in drxj_close()
11573 		pr_err("error %d\n", rc);  in drxj_close()
11583 	return rc;  in drxj_close()
11728 	int rc;  in drx_ctrl_u_code()  local
11746 		rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);  in drx_ctrl_u_code()
11747 		if (rc < 0) {  in drx_ctrl_u_code()
11749 			return rc;  in drx_ctrl_u_code()
11754 			rc = -EINVAL;  in drx_ctrl_u_code()
11774 		rc = -EINVAL;  in drx_ctrl_u_code()
11780 		rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);  in drx_ctrl_u_code()
11781 		if (rc)  in drx_ctrl_u_code()
11816 			rc = -EINVAL;  in drx_ctrl_u_code()
11833 				rc = -EIO;  in drx_ctrl_u_code()
11892 	return rc;  in drx_ctrl_u_code()
12207 	int rc = 0;  in drx39xxj_init()  local
12212 		rc = drxj_open(demod);  in drx39xxj_init()
12213 		if (rc != 0)  in drx39xxj_init()
12214 			pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);  in drx39xxj_init()
12218 	return rc;  in drx39xxj_init()