Lines Matching refs:wr_foreach
132 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); in dib3000mb_set_frontend()
133 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); in dib3000mb_set_frontend()
137 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]); in dib3000mb_set_frontend()
138 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz); in dib3000mb_set_frontend()
142 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]); in dib3000mb_set_frontend()
143 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz); in dib3000mb_set_frontend()
327 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high); in dib3000mb_set_frontend()
337 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); in dib3000mb_set_frontend()
395 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); in dib3000mb_fe_init()
397 wr_foreach(dib3000mb_reg_impulse_noise, in dib3000mb_fe_init()
400 wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain); in dib3000mb_fe_init()
404 wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase); in dib3000mb_fe_init()
406 wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration); in dib3000mb_fe_init()
408 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); in dib3000mb_fe_init()
415 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); in dib3000mb_fe_init()
433 wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs); in dib3000mb_fe_init()