528 	u16 PllCfg, i, v;  in dib0090_reset_digital()  local
546 	PllCfg = dib0090_read_reg(state, 0x21);  in dib0090_reset_digital()
549 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_reset_digital()
553 		PllCfg |= (1 << 15);  in dib0090_reset_digital()
554 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
557 		PllCfg &= ~(1 << 13);  in dib0090_reset_digital()
558 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
561 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_reset_digital()
562 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
565 		PllCfg |= (1 << 13);  in dib0090_reset_digital()
566 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
582 		PllCfg &= ~(1 << 15);  in dib0090_reset_digital()
583 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
587 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_reset_digital()
588 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
595 	u16 PllCfg;  in dib0090_fw_reset_digital()  local
618 	PllCfg = dib0090_fw_read_reg(state, 0x21);  in dib0090_fw_reset_digital()
621 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_fw_reset_digital()
624 		PllCfg |= (1 << 15);  in dib0090_fw_reset_digital()
625 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
628 		PllCfg &= ~(1 << 13);  in dib0090_fw_reset_digital()
629 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
632 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_fw_reset_digital()
633 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
636 		PllCfg |= (1 << 13);  in dib0090_fw_reset_digital()
637 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
653 		PllCfg &= ~(1 << 15);  in dib0090_fw_reset_digital()
654 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
658 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_fw_reset_digital()
659 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()