Lines Matching refs:Write_hfc
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
79 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in release_io_hfcpci()
81 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in release_io_hfcpci()
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
101 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
105 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in reset_hfcpci()
107 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in reset_hfcpci()
113 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in reset_hfcpci()
116 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in reset_hfcpci()
118 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */ in reset_hfcpci()
120 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */ in reset_hfcpci()
124 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in reset_hfcpci()
128 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in reset_hfcpci()
133 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcpci()
135 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */ in reset_hfcpci()
138 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in reset_hfcpci()
140 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in reset_hfcpci()
142 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in reset_hfcpci()
152 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in reset_hfcpci()
153 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ in reset_hfcpci()
154 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ in reset_hfcpci()
155 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ in reset_hfcpci()
156 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ in reset_hfcpci()
160 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
229 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
237 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
256 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
263 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
777 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */ in hfcpci_auxcmd()
778 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */ in hfcpci_auxcmd()
781 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */ in hfcpci_auxcmd()
783 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */ in hfcpci_auxcmd()
785 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); in hfcpci_auxcmd()
814 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in hfcpci_auxcmd()
815 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in hfcpci_auxcmd()
816 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in hfcpci_auxcmd()
817 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in hfcpci_auxcmd()
818 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in hfcpci_auxcmd()
819 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_auxcmd()
820 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_auxcmd()
970 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_interrupt()
1180 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */ in HFCPCI_l1hw()
1182 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */ in HFCPCI_l1hw()
1184 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1185 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); in HFCPCI_l1hw()
1191 Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION); in HFCPCI_l1hw()
1197 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1203 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1210 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */ in HFCPCI_l1hw()
1211 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */ in HFCPCI_l1hw()
1213 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1217 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */ in HFCPCI_l1hw()
1218 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */ in HFCPCI_l1hw()
1220 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1230 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in HFCPCI_l1hw()
1376 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); in mode_hfcpci()
1377 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in mode_hfcpci()
1378 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in mode_hfcpci()
1379 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in mode_hfcpci()
1380 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in mode_hfcpci()
1381 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in mode_hfcpci()
1382 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in mode_hfcpci()
1537 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1540 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE); in hfcpci_bh()
1542 Write_hfc(cs, HFCPCI_STATES, 4); in hfcpci_bh()
1546 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1549 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1550 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1552 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */ in hfcpci_bh()
1560 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1622 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_card_msg()
1624 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in hfcpci_card_msg()
1733 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in setup_hfcpci()
1734 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in setup_hfcpci()