Lines Matching refs:l1
182 struct hfc4s8s_l1 l1[HFC_MAX_ST]; member
304 struct hfc4s8s_l1 *l1 = iface->ifc.priv; in dch_l2l1() local
311 if (!l1->enabled) { in dch_l2l1()
315 spin_lock_irqsave(&l1->lock, flags); in dch_l2l1()
316 skb_queue_tail(&l1->d_tx_queue, skb); in dch_l2l1()
317 if ((skb_queue_len(&l1->d_tx_queue) == 1) && in dch_l2l1()
318 (l1->tx_cnt <= 0)) { in dch_l2l1()
319 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= in dch_l2l1()
321 spin_unlock_irqrestore(&l1->lock, flags); in dch_l2l1()
322 schedule_work(&l1->hw->tqueue); in dch_l2l1()
324 spin_unlock_irqrestore(&l1->lock, flags); in dch_l2l1()
328 if (!l1->enabled) in dch_l2l1()
330 if (!l1->nt_mode) { in dch_l2l1()
331 if (l1->l1_state < 6) { in dch_l2l1()
332 spin_lock_irqsave(&l1->lock, in dch_l2l1()
335 Write_hfc8(l1->hw, R_ST_SEL, in dch_l2l1()
336 l1->st_num); in dch_l2l1()
337 Write_hfc8(l1->hw, A_ST_WR_STA, in dch_l2l1()
339 mod_timer(&l1->l1_timer, in dch_l2l1()
341 spin_unlock_irqrestore(&l1->lock, in dch_l2l1()
343 } else if (l1->l1_state == 7) in dch_l2l1()
344 l1->d_if.ifc.l1l2(&l1->d_if.ifc, in dch_l2l1()
349 if (l1->l1_state != 3) { in dch_l2l1()
350 spin_lock_irqsave(&l1->lock, in dch_l2l1()
352 Write_hfc8(l1->hw, R_ST_SEL, in dch_l2l1()
353 l1->st_num); in dch_l2l1()
354 Write_hfc8(l1->hw, A_ST_WR_STA, in dch_l2l1()
356 spin_unlock_irqrestore(&l1->lock, in dch_l2l1()
358 } else if (l1->l1_state == 3) in dch_l2l1()
359 l1->d_if.ifc.l1l2(&l1->d_if.ifc, in dch_l2l1()
372 if (!l1->enabled) in dch_l2l1()
373 l1->d_if.ifc.l1l2(&l1->d_if.ifc, in dch_l2l1()
384 struct hfc4s8s_l1 *l1 = bch->l1p; in bch_l2l1() local
392 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) { in bch_l2l1()
396 spin_lock_irqsave(&l1->lock, flags); in bch_l2l1()
399 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= in bch_l2l1()
401 spin_unlock_irqrestore(&l1->lock, flags); in bch_l2l1()
402 schedule_work(&l1->hw->tqueue); in bch_l2l1()
404 spin_unlock_irqrestore(&l1->lock, flags); in bch_l2l1()
409 if (!l1->enabled) in bch_l2l1()
416 spin_lock_irqsave(&l1->lock, in bch_l2l1()
418 l1->hw->mr.timer_usg_cnt++; in bch_l2l1()
419 l1->hw->mr. in bch_l2l1()
420 fifo_slow_timer_service[l1-> in bch_l2l1()
425 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
426 (l1->st_num * 8 + in bch_l2l1()
429 wait_busy(l1->hw); in bch_l2l1()
430 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ in bch_l2l1()
431 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
432 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */ in bch_l2l1()
433 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
434 wait_busy(l1->hw); in bch_l2l1()
436 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
437 (l1->st_num * 8 + in bch_l2l1()
440 wait_busy(l1->hw); in bch_l2l1()
441 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ in bch_l2l1()
442 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
443 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */ in bch_l2l1()
444 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
446 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
447 l1->st_num); in bch_l2l1()
448 l1->hw->mr.r_ctrl0 |= in bch_l2l1()
450 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
451 l1->hw->mr.r_ctrl0); in bch_l2l1()
453 spin_unlock_irqrestore(&l1->lock, in bch_l2l1()
463 spin_lock_irqsave(&l1->lock, in bch_l2l1()
465 l1->hw->mr. in bch_l2l1()
466 fifo_rx_trans_enables[l1-> in bch_l2l1()
471 l1->hw->mr.timer_usg_cnt++; in bch_l2l1()
472 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
473 (l1->st_num * 8 + in bch_l2l1()
476 wait_busy(l1->hw); in bch_l2l1()
477 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ in bch_l2l1()
478 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
479 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ in bch_l2l1()
480 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
481 wait_busy(l1->hw); in bch_l2l1()
483 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
484 (l1->st_num * 8 + in bch_l2l1()
487 wait_busy(l1->hw); in bch_l2l1()
488 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ in bch_l2l1()
489 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
490 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ in bch_l2l1()
491 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
493 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
494 l1->st_num); in bch_l2l1()
495 l1->hw->mr.r_ctrl0 |= in bch_l2l1()
497 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
498 l1->hw->mr.r_ctrl0); in bch_l2l1()
500 spin_unlock_irqrestore(&l1->lock, in bch_l2l1()
512 spin_lock_irqsave(&l1->lock, in bch_l2l1()
514 l1->hw->mr. in bch_l2l1()
515 fifo_slow_timer_service[l1-> in bch_l2l1()
520 l1->hw->mr. in bch_l2l1()
521 fifo_rx_trans_enables[l1-> in bch_l2l1()
526 l1->hw->mr.timer_usg_cnt--; in bch_l2l1()
527 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
528 (l1->st_num * 8 + in bch_l2l1()
531 wait_busy(l1->hw); in bch_l2l1()
532 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ in bch_l2l1()
533 wait_busy(l1->hw); in bch_l2l1()
534 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
535 (l1->st_num * 8 + in bch_l2l1()
538 wait_busy(l1->hw); in bch_l2l1()
539 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ in bch_l2l1()
540 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
541 l1->st_num); in bch_l2l1()
542 l1->hw->mr.r_ctrl0 &= in bch_l2l1()
544 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
545 l1->hw->mr.r_ctrl0); in bch_l2l1()
546 spin_unlock_irqrestore(&l1->lock, in bch_l2l1()
570 if (l1->hw->mr.timer_usg_cnt) { in bch_l2l1()
571 Write_hfc8(l1->hw, R_IRQMSK_MISC, in bch_l2l1()
574 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); in bch_l2l1()
585 if (!l1->enabled) in bch_l2l1()
594 hfc_l1_timer(struct hfc4s8s_l1 *l1) in hfc_l1_timer() argument
598 if (!l1->enabled) in hfc_l1_timer()
601 spin_lock_irqsave(&l1->lock, flags); in hfc_l1_timer()
602 if (l1->nt_mode) { in hfc_l1_timer()
603 l1->l1_state = 1; in hfc_l1_timer()
604 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
605 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); in hfc_l1_timer()
606 spin_unlock_irqrestore(&l1->lock, flags); in hfc_l1_timer()
607 l1->d_if.ifc.l1l2(&l1->d_if.ifc, in hfc_l1_timer()
609 spin_lock_irqsave(&l1->lock, flags); in hfc_l1_timer()
610 l1->l1_state = 1; in hfc_l1_timer()
611 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); in hfc_l1_timer()
612 spin_unlock_irqrestore(&l1->lock, flags); in hfc_l1_timer()
615 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
616 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); in hfc_l1_timer()
617 spin_unlock_irqrestore(&l1->lock, flags); in hfc_l1_timer()
618 l1->d_if.ifc.l1l2(&l1->d_if.ifc, in hfc_l1_timer()
620 spin_lock_irqsave(&l1->lock, flags); in hfc_l1_timer()
621 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
622 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); in hfc_l1_timer()
623 spin_unlock_irqrestore(&l1->lock, flags); in hfc_l1_timer()
741 struct hfc4s8s_l1 *l1 = bch->l1p; in rx_b_frame() local
744 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) in rx_b_frame()
749 Write_hfc8(l1->hw, R_FIFO, in rx_b_frame()
750 (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); in rx_b_frame()
751 wait_busy(l1->hw); in rx_b_frame()
754 f1 = Read_hfc8_stable(l1->hw, A_F1); in rx_b_frame()
755 f2 = Read_hfc8(l1->hw, A_F2); in rx_b_frame()
759 z1 = Read_hfc16_stable(l1->hw, A_Z1); in rx_b_frame()
760 z2 = Read_hfc16(l1->hw, A_Z2); in rx_b_frame()
794 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in rx_b_frame()
795 wait_busy(l1->hw); in rx_b_frame()
798 SetRegAddr(l1->hw, A_FIFO_DATA0); in rx_b_frame()
802 fRead_hfc32(l1->hw); in rx_b_frame()
808 *(bch->rx_ptr++) = fRead_hfc8(l1->hw); in rx_b_frame()
812 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); in rx_b_frame()
813 wait_busy(l1->hw); in rx_b_frame()
895 struct hfc4s8s_l1 *l1 = bch->l1p; in tx_b_frame() local
900 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) in tx_b_frame()
904 Write_hfc8(l1->hw, R_FIFO, in tx_b_frame()
905 (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); in tx_b_frame()
906 wait_busy(l1->hw); in tx_b_frame()
910 hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT; in tx_b_frame()
912 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT); in tx_b_frame()
922 l1->hw->mr.fifo_slow_timer_service[l1-> in tx_b_frame()
932 l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= in tx_b_frame()
935 l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= in tx_b_frame()
938 max = Read_hfc16_stable(l1->hw, A_Z2); in tx_b_frame()
939 max -= Read_hfc16(l1->hw, A_Z1); in tx_b_frame()
953 SetRegAddr(l1->hw, A_FIFO_DATA0); in tx_b_frame()
955 fWrite_hfc32(l1->hw, *(unsigned long *) cp); in tx_b_frame()
961 fWrite_hfc8(l1->hw, *cp++); in tx_b_frame()
966 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); in tx_b_frame()
974 Write_hfc8(l1->hw, R_FIFO, in tx_b_frame()
975 (l1->st_num * 8 + in tx_b_frame()
977 wait_busy(l1->hw); in tx_b_frame()
999 l1p = hw->l1; in hfc4s8s_bh()
1107 l1p = hw->l1; in hfc4s8s_bh()
1292 hw->l1[i].enabled = 1; in hfc_hardware_enable()
1293 hw->l1[i].nt_mode = nt_mode; in hfc_hardware_enable()
1327 (&hw->l1[i].d_if, hw->l1[i].b_table, if_name, in hfc_hardware_enable()
1330 hw->l1[i].enabled = 0; in hfc_hardware_enable()
1352 hw->l1[i].enabled = 0; in hfc_hardware_enable()
1353 hisax_unregister(&hw->l1[i].d_if); in hfc_hardware_enable()
1354 del_timer(&hw->l1[i].l1_timer); in hfc_hardware_enable()
1355 skb_queue_purge(&hw->l1[i].d_tx_queue); in hfc_hardware_enable()
1356 skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue); in hfc_hardware_enable()
1357 skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue); in hfc_hardware_enable()
1396 l1p = hw->l1 + i; in setup_instance()
1404 l1p->d_if.ifc.priv = hw->l1 + i; in setup_instance()
1410 l1p->b_ch[0].l1p = hw->l1 + i; in setup_instance()
1418 l1p->b_ch[1].l1p = hw->l1 + i; in setup_instance()