Lines Matching refs:Write_hfc8
215 Write_hfc8(hfc4s8s_hw *a, u_char b, u_char c) in Write_hfc8() function
335 Write_hfc8(l1->hw, R_ST_SEL, in dch_l2l1()
337 Write_hfc8(l1->hw, A_ST_WR_STA, in dch_l2l1()
352 Write_hfc8(l1->hw, R_ST_SEL, in dch_l2l1()
354 Write_hfc8(l1->hw, A_ST_WR_STA, in dch_l2l1()
425 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
430 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ in bch_l2l1()
431 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
432 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */ in bch_l2l1()
433 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
436 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
441 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */ in bch_l2l1()
442 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
443 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */ in bch_l2l1()
444 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
446 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
450 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
472 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
477 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ in bch_l2l1()
478 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
479 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ in bch_l2l1()
480 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
483 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
488 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */ in bch_l2l1()
489 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */ in bch_l2l1()
490 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ in bch_l2l1()
491 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in bch_l2l1()
493 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
497 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
527 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
532 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */ in bch_l2l1()
534 Write_hfc8(l1->hw, R_FIFO, in bch_l2l1()
539 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */ in bch_l2l1()
540 Write_hfc8(l1->hw, R_ST_SEL, in bch_l2l1()
544 Write_hfc8(l1->hw, A_ST_CTRL0, in bch_l2l1()
571 Write_hfc8(l1->hw, R_IRQMSK_MISC, in bch_l2l1()
574 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); in bch_l2l1()
604 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
605 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); in hfc_l1_timer()
611 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); in hfc_l1_timer()
615 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
616 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); in hfc_l1_timer()
621 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); in hfc_l1_timer()
622 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); in hfc_l1_timer()
643 Write_hfc8(l1p->hw, R_FIFO, in rx_d_frame()
669 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); in rx_d_frame()
680 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2); in rx_d_frame()
695 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); in rx_d_frame()
714 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ in rx_d_frame()
749 Write_hfc8(l1->hw, R_FIFO, in rx_b_frame()
794 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */ in rx_b_frame()
812 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); in rx_b_frame()
849 Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4)); in tx_d_frame()
881 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */ in tx_d_frame()
904 Write_hfc8(l1->hw, R_FIFO, in tx_b_frame()
966 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1); in tx_b_frame()
974 Write_hfc8(l1->hw, R_FIFO, in tx_b_frame()
1008 Write_hfc8(l1p->hw, R_ST_SEL, in hfc4s8s_bh()
1037 Write_hfc8(hw, A_ST_WR_STA, in hfc4s8s_bh()
1050 Write_hfc8(l1p->hw, R_ST_SEL, in hfc4s8s_bh()
1236 Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */ in chipreset()
1237 Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */ in chipreset()
1238 Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */ in chipreset()
1239 Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */ in chipreset()
1244 Write_hfc8(hw, R_CIRM, 0); /* disable reset */ in chipreset()
1247 Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */ in chipreset()
1248 Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */ in chipreset()
1250 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */ in chipreset()
1251 Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */ in chipreset()
1272 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); in hfc_hardware_enable()
1274 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); in hfc_hardware_enable()
1275 Write_hfc8(hw, R_PWM_MD, 0x80); in hfc_hardware_enable()
1276 Write_hfc8(hw, R_PWM1, 26); in hfc_hardware_enable()
1278 Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC); in hfc_hardware_enable()
1283 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg); in hfc_hardware_enable()
1284 Write_hfc8(hw, R_ST_SEL, i); in hfc_hardware_enable()
1285 Write_hfc8(hw, A_ST_CLK_DLY, in hfc_hardware_enable()
1288 Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0); in hfc_hardware_enable()
1289 Write_hfc8(hw, A_ST_CTRL2, 3); in hfc_hardware_enable()
1290 Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */ in hfc_hardware_enable()
1297 Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */ in hfc_hardware_enable()
1299 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ in hfc_hardware_enable()
1300 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ in hfc_hardware_enable()
1301 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ in hfc_hardware_enable()
1302 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ in hfc_hardware_enable()
1306 Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */ in hfc_hardware_enable()
1308 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ in hfc_hardware_enable()
1309 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ in hfc_hardware_enable()
1310 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ in hfc_hardware_enable()
1311 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ in hfc_hardware_enable()
1315 Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */ in hfc_hardware_enable()
1317 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */ in hfc_hardware_enable()
1318 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */ in hfc_hardware_enable()
1319 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */ in hfc_hardware_enable()
1320 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */ in hfc_hardware_enable()
1332 Write_hfc8(hw, R_SCI_MSK, in hfc_hardware_enable()
1342 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); in hfc_hardware_enable()
1348 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); in hfc_hardware_enable()