Lines Matching refs:DC21285_ARMCSR_BASE
70 #define DC21285_ARMCSR_BASE 0x42000000 macro
310 c4_poke(card, DC21285_ARMCSR_BASE + CHAN_1_CONTROL, 0); in c4_reset()
311 c4_poke(card, DC21285_ARMCSR_BASE + CHAN_2_CONTROL, 0); in c4_reset()
334 c4_poke(card, DC21285_ARMCSR_BASE + CHAN_1_CONTROL, 0); in c4_detect()
335 c4_poke(card, DC21285_ARMCSR_BASE + CHAN_2_CONTROL, 0); in c4_detect()
343 if (c4_poke(card, DC21285_ARMCSR_BASE + DBELL_SA_MASK, 0)) return 5; in c4_detect()
344 if (c4_poke(card, DC21285_ARMCSR_BASE + DBELL_PCI_MASK, 0)) return 6; in c4_detect()
345 if (c4_poke(card, DC21285_ARMCSR_BASE + SA_CONTROL, SA_CTL_ALLRIGHT)) in c4_detect()
347 if (c4_poke(card, DC21285_ARMCSR_BASE + XBUS_CYCLE, INIT_XBUS_CYCLE)) in c4_detect()
349 if (c4_poke(card, DC21285_ARMCSR_BASE + XBUS_STROBE, INIT_XBUS_STROBE)) in c4_detect()
351 if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_TIMING, 0)) return 9; in c4_detect()
367 if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_TIMING, DRAM_TIMING_DEF)) in c4_detect()
370 if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_0, DRAM_AD_SZ_DEF0)) in c4_detect()
372 if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_1, DRAM_AD_SZ_NULL)) in c4_detect()
374 if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_2, DRAM_AD_SZ_NULL)) in c4_detect()
376 if (c4_poke(card, DC21285_ARMCSR_BASE + DRAM_ADDR_SIZE_3, DRAM_AD_SZ_NULL)) in c4_detect()