43 static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,  in ab_irqctl_writereg()  argument
46 	irq_reg_writel(gc, val, reg);  in ab_irqctl_writereg()
49 static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)  in ab_irqctl_readreg()  argument
51 	return irq_reg_readl(gc, reg);  in ab_irqctl_readreg()
56 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in tb10x_irq_set_type()  local
61 	irq_gc_lock(gc);  in tb10x_irq_set_type()
63 	mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;  in tb10x_irq_set_type()
64 	pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;  in tb10x_irq_set_type()
82 		irq_gc_unlock(gc);  in tb10x_irq_set_type()
91 	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);  in tb10x_irq_set_type()
92 	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);  in tb10x_irq_set_type()
93 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);  in tb10x_irq_set_type()
95 	irq_gc_unlock(gc);  in tb10x_irq_set_type()
113 	struct irq_chip_generic *gc;  in of_tb10x_init_irq()  local
155 	gc = domain->gc->gc[0];  in of_tb10x_init_irq()
156 	gc->reg_base                         = reg_base;  in of_tb10x_init_irq()
158 	gc->chip_types[0].type               = IRQ_TYPE_LEVEL_MASK;  in of_tb10x_init_irq()
159 	gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;  in of_tb10x_init_irq()
160 	gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;  in of_tb10x_init_irq()
161 	gc->chip_types[0].chip.irq_set_type  = tb10x_irq_set_type;  in of_tb10x_init_irq()
162 	gc->chip_types[0].regs.mask          = AB_IRQCTL_INT_ENABLE;  in of_tb10x_init_irq()
164 	gc->chip_types[1].type               = IRQ_TYPE_EDGE_BOTH;  in of_tb10x_init_irq()
165 	gc->chip_types[1].chip.name          = gc->chip_types[0].chip.name;  in of_tb10x_init_irq()
166 	gc->chip_types[1].chip.irq_ack       = irq_gc_ack_set_bit;  in of_tb10x_init_irq()
167 	gc->chip_types[1].chip.irq_mask      = irq_gc_mask_clr_bit;  in of_tb10x_init_irq()
168 	gc->chip_types[1].chip.irq_unmask    = irq_gc_mask_set_bit;  in of_tb10x_init_irq()
169 	gc->chip_types[1].chip.irq_set_type  = tb10x_irq_set_type;  in of_tb10x_init_irq()
170 	gc->chip_types[1].regs.ack           = AB_IRQCTL_INT_STATUS;  in of_tb10x_init_irq()
171 	gc->chip_types[1].regs.mask          = AB_IRQCTL_INT_ENABLE;  in of_tb10x_init_irq()
172 	gc->chip_types[1].handler            = handle_edge_irq;  in of_tb10x_init_irq()
181 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);  in of_tb10x_init_irq()
182 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);  in of_tb10x_init_irq()
183 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);  in of_tb10x_init_irq()
184 	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);  in of_tb10x_init_irq()