53 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,  in sunxi_sc_nmi_write()  argument
56 	irq_reg_writel(gc, val, off);  in sunxi_sc_nmi_write()
59 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)  in sunxi_sc_nmi_read()  argument
61 	return irq_reg_readl(gc, off);  in sunxi_sc_nmi_read()
77 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in sunxi_sc_nmi_set_type()  local
78 	struct irq_chip_type *ct = gc->chip_types;  in sunxi_sc_nmi_set_type()
84 	irq_gc_lock(gc);  in sunxi_sc_nmi_set_type()
101 		irq_gc_unlock(gc);  in sunxi_sc_nmi_set_type()
110 	for (i = 0; i < gc->num_ct; i++, ct++)  in sunxi_sc_nmi_set_type()
114 	src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);  in sunxi_sc_nmi_set_type()
117 	sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);  in sunxi_sc_nmi_set_type()
119 	irq_gc_unlock(gc);  in sunxi_sc_nmi_set_type()
128 	struct irq_chip_generic *gc;  in sunxi_sc_nmi_irq_init()  local
155 	gc = irq_get_domain_generic_chip(domain, 0);  in sunxi_sc_nmi_irq_init()
156 	gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));  in sunxi_sc_nmi_irq_init()
157 	if (IS_ERR(gc->reg_base)) {  in sunxi_sc_nmi_irq_init()
159 		ret = PTR_ERR(gc->reg_base);  in sunxi_sc_nmi_irq_init()
163 	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;  in sunxi_sc_nmi_irq_init()
164 	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;  in sunxi_sc_nmi_irq_init()
165 	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;  in sunxi_sc_nmi_irq_init()
166 	gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;  in sunxi_sc_nmi_irq_init()
167 	gc->chip_types[0].chip.irq_set_type	= sunxi_sc_nmi_set_type;  in sunxi_sc_nmi_irq_init()
168 	gc->chip_types[0].chip.flags		= IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;  in sunxi_sc_nmi_irq_init()
169 	gc->chip_types[0].regs.ack		= reg_offs->pend;  in sunxi_sc_nmi_irq_init()
170 	gc->chip_types[0].regs.mask		= reg_offs->enable;  in sunxi_sc_nmi_irq_init()
171 	gc->chip_types[0].regs.type		= reg_offs->ctrl;  in sunxi_sc_nmi_irq_init()
173 	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;  in sunxi_sc_nmi_irq_init()
174 	gc->chip_types[1].chip.name		= gc->chip_types[0].chip.name;  in sunxi_sc_nmi_irq_init()
175 	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;  in sunxi_sc_nmi_irq_init()
176 	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;  in sunxi_sc_nmi_irq_init()
177 	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;  in sunxi_sc_nmi_irq_init()
178 	gc->chip_types[1].chip.irq_set_type	= sunxi_sc_nmi_set_type;  in sunxi_sc_nmi_irq_init()
179 	gc->chip_types[1].regs.ack		= reg_offs->pend;  in sunxi_sc_nmi_irq_init()
180 	gc->chip_types[1].regs.mask		= reg_offs->enable;  in sunxi_sc_nmi_irq_init()
181 	gc->chip_types[1].regs.type		= reg_offs->ctrl;  in sunxi_sc_nmi_irq_init()
182 	gc->chip_types[1].handler		= handle_edge_irq;  in sunxi_sc_nmi_irq_init()
184 	sunxi_sc_nmi_write(gc, reg_offs->enable, 0);  in sunxi_sc_nmi_irq_init()
185 	sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);  in sunxi_sc_nmi_irq_init()