Lines Matching refs:d
63 static inline unsigned int gic_irq(struct irq_data *d) in gic_irq() argument
65 return d->hwirq; in gic_irq()
68 static inline int gic_irq_in_rdist(struct irq_data *d) in gic_irq_in_rdist() argument
70 return gic_irq(d) < 32; in gic_irq_in_rdist()
73 static inline void __iomem *gic_dist_base(struct irq_data *d) in gic_dist_base() argument
75 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
78 if (d->hwirq <= 1023) /* SPI -> dist_base */ in gic_dist_base()
160 static int gic_peek_irq(struct irq_data *d, u32 offset) in gic_peek_irq() argument
162 u32 mask = 1 << (gic_irq(d) % 32); in gic_peek_irq()
165 if (gic_irq_in_rdist(d)) in gic_peek_irq()
170 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); in gic_peek_irq()
173 static void gic_poke_irq(struct irq_data *d, u32 offset) in gic_poke_irq() argument
175 u32 mask = 1 << (gic_irq(d) % 32); in gic_poke_irq()
179 if (gic_irq_in_rdist(d)) { in gic_poke_irq()
187 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); in gic_poke_irq()
191 static void gic_mask_irq(struct irq_data *d) in gic_mask_irq() argument
193 gic_poke_irq(d, GICD_ICENABLER); in gic_mask_irq()
196 static void gic_eoimode1_mask_irq(struct irq_data *d) in gic_eoimode1_mask_irq() argument
198 gic_mask_irq(d); in gic_eoimode1_mask_irq()
207 if (irqd_is_forwarded_to_vcpu(d)) in gic_eoimode1_mask_irq()
208 gic_poke_irq(d, GICD_ICACTIVER); in gic_eoimode1_mask_irq()
211 static void gic_unmask_irq(struct irq_data *d) in gic_unmask_irq() argument
213 gic_poke_irq(d, GICD_ISENABLER); in gic_unmask_irq()
216 static int gic_irq_set_irqchip_state(struct irq_data *d, in gic_irq_set_irqchip_state() argument
221 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ in gic_irq_set_irqchip_state()
241 gic_poke_irq(d, reg); in gic_irq_set_irqchip_state()
245 static int gic_irq_get_irqchip_state(struct irq_data *d, in gic_irq_get_irqchip_state() argument
248 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
253 *val = gic_peek_irq(d, GICD_ISPENDR); in gic_irq_get_irqchip_state()
257 *val = gic_peek_irq(d, GICD_ISACTIVER); in gic_irq_get_irqchip_state()
261 *val = !gic_peek_irq(d, GICD_ISENABLER); in gic_irq_get_irqchip_state()
271 static void gic_eoi_irq(struct irq_data *d) in gic_eoi_irq() argument
273 gic_write_eoir(gic_irq(d)); in gic_eoi_irq()
276 static void gic_eoimode1_eoi_irq(struct irq_data *d) in gic_eoimode1_eoi_irq() argument
282 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) in gic_eoimode1_eoi_irq()
284 gic_write_dir(gic_irq(d)); in gic_eoimode1_eoi_irq()
287 static int gic_set_type(struct irq_data *d, unsigned int type) in gic_set_type() argument
289 unsigned int irq = gic_irq(d); in gic_set_type()
302 if (gic_irq_in_rdist(d)) { in gic_set_type()
313 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) in gic_irq_set_vcpu_affinity() argument
316 irqd_set_forwarded_to_vcpu(d); in gic_irq_set_vcpu_affinity()
318 irqd_clr_forwarded_to_vcpu(d); in gic_irq_set_vcpu_affinity()
626 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, in gic_set_affinity() argument
634 if (gic_irq_in_rdist(d)) in gic_set_affinity()
638 enabled = gic_peek_irq(d, GICD_ISENABLER); in gic_set_affinity()
640 gic_mask_irq(d); in gic_set_affinity()
642 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); in gic_set_affinity()
652 gic_unmask_irq(d); in gic_set_affinity()
717 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, in gic_irq_domain_map() argument
738 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
744 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
752 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
759 static int gic_irq_domain_translate(struct irq_domain *d, in gic_irq_domain_translate() argument
813 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); in gic_irq_domain_free() local
815 irq_domain_reset_irq_data(d); in gic_irq_domain_free()