Lines Matching refs:gc
38 struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); in dw_apb_ictl_handler() local
39 u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); in dw_apb_ictl_handler()
43 u32 virq = irq_find_mapping(d, gc->irq_base + hwirq); in dw_apb_ictl_handler()
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); in dw_apb_ictl_resume() local
59 irq_gc_lock(gc); in dw_apb_ictl_resume()
60 writel_relaxed(~0, gc->reg_base + ct->regs.enable); in dw_apb_ictl_resume()
61 writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); in dw_apb_ictl_resume()
62 irq_gc_unlock(gc); in dw_apb_ictl_resume()
74 struct irq_chip_generic *gc; in dw_apb_ictl_init() local
140 gc = irq_get_domain_generic_chip(domain, i * 32); in dw_apb_ictl_init()
141 gc->reg_base = iobase + i * APB_INT_BASE_OFFSET; in dw_apb_ictl_init()
142 gc->chip_types[0].regs.mask = APB_INT_MASK_L; in dw_apb_ictl_init()
143 gc->chip_types[0].regs.enable = APB_INT_ENABLE_L; in dw_apb_ictl_init()
144 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in dw_apb_ictl_init()
145 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; in dw_apb_ictl_init()
146 gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; in dw_apb_ictl_init()