90 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_mask()  local
97 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_mask()
98 	irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_mask()
99 	gc->mask_cache &= ~d->mask;  in aic5_mask()
107 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_unmask()  local
114 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);  in aic5_unmask()
115 	irq_reg_writel(gc, 1, AT91_AIC5_IECR);  in aic5_unmask()
116 	gc->mask_cache |= d->mask;  in aic5_unmask()
156 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_suspend()
158 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_suspend()  local
165 		if ((mask & gc->mask_cache) == (mask & gc->wake_active))  in aic5_suspend()
168 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_suspend()
169 		if (mask & gc->wake_active)  in aic5_suspend()
180 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_resume()
182 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_resume()  local
189 		if ((mask & gc->mask_cache) == (mask & gc->wake_active))  in aic5_resume()
192 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_resume()
193 		if (mask & gc->mask_cache)  in aic5_resume()
204 	struct irq_domain_chip_generic *dgc = domain->gc;  in aic5_pm_shutdown()
206 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic5_pm_shutdown()  local
211 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_pm_shutdown()
225 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);  in aic5_hw_init()  local
233 		irq_reg_writel(gc, 0, AT91_AIC5_EOICR);  in aic5_hw_init()
240 	irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);  in aic5_hw_init()
243 	irq_reg_writel(gc, 0, AT91_AIC5_DCR);  in aic5_hw_init()
247 		irq_reg_writel(gc, i, AT91_AIC5_SSR);  in aic5_hw_init()
248 		irq_reg_writel(gc, i, AT91_AIC5_SVR);  in aic5_hw_init()
249 		irq_reg_writel(gc, 1, AT91_AIC5_IDCR);  in aic5_hw_init()
250 		irq_reg_writel(gc, 1, AT91_AIC5_ICCR);  in aic5_hw_init()
303 	struct irq_chip_generic *gc;  in aic5_of_init()  local
324 		gc = irq_get_domain_generic_chip(domain, i * 32);  in aic5_of_init()
326 		gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;  in aic5_of_init()
327 		gc->chip_types[0].chip.irq_mask = aic5_mask;  in aic5_of_init()
328 		gc->chip_types[0].chip.irq_unmask = aic5_unmask;  in aic5_of_init()
329 		gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;  in aic5_of_init()
330 		gc->chip_types[0].chip.irq_set_type = aic5_set_type;  in aic5_of_init()
331 		gc->chip_types[0].chip.irq_suspend = aic5_suspend;  in aic5_of_init()
332 		gc->chip_types[0].chip.irq_resume = aic5_resume;  in aic5_of_init()
333 		gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;  in aic5_of_init()