Lines Matching refs:u8
26 u8 d0, mr; /* Mode register 1/2*/
27 u8 d1, sr; /* Status register */
28 u8 d2, r1; /* reserved */
29 u8 d3, rhr; /* Receive holding register (R) */
30 u8 junk[8]; /* other crap for block control */
33 u8 d0, mr; /* Mode register 1/2 */
34 u8 d1, csr; /* Clock select register */
35 u8 d2, cr; /* Command register */
36 u8 d3, thr; /* Transmit holding register */
37 u8 junk[8]; /* other crap for block control */
51 u8 d0, mra; /* Mode register 1/2 (a) */
52 u8 d1, sra; /* Status register (a) */
53 u8 d2, r1; /* reserved */
54 u8 d3, rhra; /* Receive holding register (a) */
55 u8 d4, ipcr; /* Input port change register of block */
56 u8 d5, isr; /* Interrupt status register of block */
57 u8 d6, ctur; /* Counter timer upper register of block */
58 u8 d7, ctlr; /* Counter timer lower register of block */
59 u8 d8, mrb; /* Mode register 1/2 (b) */
60 u8 d9, srb; /* Status register (b) */
61 u8 da, r2; /* reserved */
62 u8 db, rhrb; /* Receive holding register (b) */
63 u8 dc, r3; /* reserved */
64 u8 dd, ip; /* Input port register of block */
65 u8 de, ctg; /* Start counter timer of block */
66 u8 df, cts; /* Stop counter timer of block */
69 u8 d0, mra; /* Mode register 1/2 (a) */
70 u8 d1, csra; /* Clock select register (a) */
71 u8 d2, cra; /* Command register (a) */
72 u8 d3, thra; /* Transmit holding register (a) */
73 u8 d4, acr; /* Auxiliary control register of block */
74 u8 d5, imr; /* Interrupt mask register of block */
75 u8 d6, ctu; /* Counter timer upper register of block */
76 u8 d7, ctl; /* Counter timer lower register of block */
77 u8 d8, mrb; /* Mode register 1/2 (b) */
78 u8 d9, csrb; /* Clock select register (a) */
79 u8 da, crb; /* Command register (b) */
80 u8 db, thrb; /* Transmit holding register (b) */
81 u8 dc, r1; /* reserved */
82 u8 dd, opcr; /* Output port configuration register of block */
83 u8 de, r2; /* reserved */
84 u8 df, r3; /* reserved */