57 static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,  in smmu_writel()  argument
60 	writel(value, smmu->regs + offset);  in smmu_writel()
170 	u32 value;  in smmu_flush_ptc()  local
176 		value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;  in smmu_flush_ptc()
178 		value = 0;  in smmu_flush_ptc()
180 		smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);  in smmu_flush_ptc()
183 	value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;  in smmu_flush_ptc()
184 	smmu_writel(smmu, value, SMMU_PTC_FLUSH);  in smmu_flush_ptc()
195 	u32 value;  in smmu_flush_tlb_asid()  local
197 	value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |  in smmu_flush_tlb_asid()
199 	smmu_writel(smmu, value, SMMU_TLB_FLUSH);  in smmu_flush_tlb_asid()
206 	u32 value;  in smmu_flush_tlb_section()  local
208 	value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |  in smmu_flush_tlb_section()
210 	smmu_writel(smmu, value, SMMU_TLB_FLUSH);  in smmu_flush_tlb_section()
217 	u32 value;  in smmu_flush_tlb_group()  local
219 	value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |  in smmu_flush_tlb_group()
221 	smmu_writel(smmu, value, SMMU_TLB_FLUSH);  in smmu_flush_tlb_group()
332 	u32 value;  in tegra_smmu_enable()  local
340 		value = smmu_readl(smmu, client->smmu.reg);  in tegra_smmu_enable()
341 		value |= BIT(client->smmu.bit);  in tegra_smmu_enable()
342 		smmu_writel(smmu, value, client->smmu.reg);  in tegra_smmu_enable()
347 		value = smmu_readl(smmu, group->reg);  in tegra_smmu_enable()
348 		value &= ~SMMU_ASID_MASK;  in tegra_smmu_enable()
349 		value |= SMMU_ASID_VALUE(asid);  in tegra_smmu_enable()
350 		value |= SMMU_ASID_ENABLE;  in tegra_smmu_enable()
351 		smmu_writel(smmu, value, group->reg);  in tegra_smmu_enable()
360 	u32 value;  in tegra_smmu_disable()  local
364 		value = smmu_readl(smmu, group->reg);  in tegra_smmu_disable()
365 		value &= ~SMMU_ASID_MASK;  in tegra_smmu_disable()
366 		value |= SMMU_ASID_VALUE(asid);  in tegra_smmu_disable()
367 		value &= ~SMMU_ASID_ENABLE;  in tegra_smmu_disable()
368 		smmu_writel(smmu, value, group->reg);  in tegra_smmu_disable()
377 		value = smmu_readl(smmu, client->smmu.reg);  in tegra_smmu_disable()
378 		value &= ~BIT(client->smmu.bit);  in tegra_smmu_disable()
379 		smmu_writel(smmu, value, client->smmu.reg);  in tegra_smmu_disable()
386 	u32 value;  in tegra_smmu_as_prepare()  local
413 	value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);  in tegra_smmu_as_prepare()
414 	smmu_writel(smmu, value, SMMU_PTB_DATA);  in tegra_smmu_as_prepare()
501 			       u32 value)  in tegra_smmu_set_pde()  argument
509 	pd[pd_index] = value;  in tegra_smmu_set_pde()
770 	u32 value;  in tegra_smmu_swgroups_show()  local
780 		value = smmu_readl(smmu, group->reg);  in tegra_smmu_swgroups_show()
782 		if (value & SMMU_ASID_ENABLE)  in tegra_smmu_swgroups_show()
787 		asid = value & SMMU_ASID_MASK;  in tegra_smmu_swgroups_show()
812 	u32 value;  in tegra_smmu_clients_show()  local
821 		value = smmu_readl(smmu, client->smmu.reg);  in tegra_smmu_clients_show()
823 		if (value & BIT(client->smmu.bit))  in tegra_smmu_clients_show()
869 	u32 value;  in tegra_smmu_probe()  local
910 	value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);  in tegra_smmu_probe()
913 		value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);  in tegra_smmu_probe()
915 	smmu_writel(smmu, value, SMMU_PTC_CONFIG);  in tegra_smmu_probe()
917 	value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |  in tegra_smmu_probe()
921 		value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;  in tegra_smmu_probe()
923 	smmu_writel(smmu, value, SMMU_TLB_CONFIG);  in tegra_smmu_probe()