80 		writel_relaxed(__val >> 32, __addr + 4);	\
81 		writel_relaxed(__val, __addr);			\
544 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);  in __arm_smmu_tlb_sync()
573 		writel_relaxed(ARM_SMMU_CB_ASID(cfg),  in arm_smmu_tlb_inv_context()
577 		writel_relaxed(ARM_SMMU_CB_VMID(cfg),  in arm_smmu_tlb_inv_context()
600 			writel_relaxed(iova, reg);  in arm_smmu_tlb_inv_range_nosync()
617 		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);  in arm_smmu_tlb_inv_range_nosync()
675 		writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);  in arm_smmu_context_fault()
729 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));  in arm_smmu_init_context_bank()
747 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));  in arm_smmu_init_context_bank()
767 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
771 			writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);  in arm_smmu_init_context_bank()
775 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
781 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);  in arm_smmu_init_context_bank()
783 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);  in arm_smmu_init_context_bank()
793 	writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_init_context_bank()
941 	writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_destroy_domain_context()
1027 		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));  in arm_smmu_master_configure_smrs()
1054 		writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));  in arm_smmu_master_free_smrs()
1080 		writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));  in arm_smmu_domain_add_master()
1104 		writel_relaxed(S2CR_TYPE_BYPASS,  in arm_smmu_domain_remove_master()
1223 		writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);  in arm_smmu_iova_to_phys_hard()
1469 		writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));  in arm_smmu_device_reset()
1470 		writel_relaxed(S2CR_TYPE_BYPASS,  in arm_smmu_device_reset()
1477 		writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_device_reset()
1478 		writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_device_reset()
1482 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);  in arm_smmu_device_reset()
1483 	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);  in arm_smmu_device_reset()
1602 		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));  in arm_smmu_device_cfg_probe()