Lines Matching refs:gr0_base
542 void __iomem *gr0_base = ARM_SMMU_GR0(smmu); in __arm_smmu_tlb_sync() local
544 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); in __arm_smmu_tlb_sync()
545 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) in __arm_smmu_tlb_sync()
684 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); in arm_smmu_global_fault() local
686 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
687 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); in arm_smmu_global_fault()
688 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); in arm_smmu_global_fault()
689 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); in arm_smmu_global_fault()
700 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
992 void __iomem *gr0_base = ARM_SMMU_GR0(smmu); in arm_smmu_master_configure_smrs() local
1027 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); in arm_smmu_master_configure_smrs()
1044 void __iomem *gr0_base = ARM_SMMU_GR0(smmu); in arm_smmu_master_free_smrs() local
1054 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); in arm_smmu_master_free_smrs()
1067 void __iomem *gr0_base = ARM_SMMU_GR0(smmu); in arm_smmu_domain_add_master() local
1080 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); in arm_smmu_domain_add_master()
1091 void __iomem *gr0_base = ARM_SMMU_GR0(smmu); in arm_smmu_domain_remove_master() local
1105 gr0_base + ARM_SMMU_GR0_S2CR(idx)); in arm_smmu_domain_remove_master()
1458 void __iomem *gr0_base = ARM_SMMU_GR0(smmu); in arm_smmu_device_reset() local
1469 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); in arm_smmu_device_reset()
1471 gr0_base + ARM_SMMU_GR0_S2CR(i)); in arm_smmu_device_reset()
1482 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); in arm_smmu_device_reset()
1483 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); in arm_smmu_device_reset()
1529 void __iomem *gr0_base = ARM_SMMU_GR0(smmu); in arm_smmu_device_cfg_probe() local
1537 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); in arm_smmu_device_cfg_probe()
1602 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); in arm_smmu_device_cfg_probe()
1603 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); in arm_smmu_device_cfg_probe()
1623 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); in arm_smmu_device_cfg_probe()
1644 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); in arm_smmu_device_cfg_probe()