284 	struct arm_smmu_master_cfg	cfg;  member
333 #define ARM_SMMU_CB_ASID(cfg)		((cfg)->cbndx)  argument
334 #define ARM_SMMU_CB_VMID(cfg)		((cfg)->cbndx + 1)  argument
346 	struct arm_smmu_cfg		cfg;  member
423 	struct arm_smmu_master_cfg *cfg = NULL;  in find_smmu_master_cfg()  local
427 		cfg = iommu_group_get_iommudata(group);  in find_smmu_master_cfg()
431 	return cfg;  in find_smmu_master_cfg()
486 	master->cfg.num_streamids	= masterspec->args_count;  in register_smmu_master()
488 	for (i = 0; i < master->cfg.num_streamids; ++i) {  in register_smmu_master()
498 		master->cfg.streamids[i] = streamid;  in register_smmu_master()
566 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_tlb_inv_context()  local
568 	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;  in arm_smmu_tlb_inv_context()
572 		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_tlb_inv_context()
573 		writel_relaxed(ARM_SMMU_CB_ASID(cfg),  in arm_smmu_tlb_inv_context()
577 		writel_relaxed(ARM_SMMU_CB_VMID(cfg),  in arm_smmu_tlb_inv_context()
588 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_tlb_inv_range_nosync()  local
590 	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;  in arm_smmu_tlb_inv_range_nosync()
594 		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_tlb_inv_range_nosync()
599 			iova |= ARM_SMMU_CB_ASID(cfg);  in arm_smmu_tlb_inv_range_nosync()
604 			iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;  in arm_smmu_tlb_inv_range_nosync()
610 		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_tlb_inv_range_nosync()
617 		writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);  in arm_smmu_tlb_inv_range_nosync()
634 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_context_fault()  local
638 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_context_fault()
665 		    iova, fsynr, cfg->cbndx);  in arm_smmu_context_fault()
710 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_init_context_bank()  local
715 	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;  in arm_smmu_init_context_bank()
716 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_init_context_bank()
729 		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));  in arm_smmu_init_context_bank()
733 	reg = cfg->cbar;  in arm_smmu_init_context_bank()
735 		reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;  in arm_smmu_init_context_bank()
745 		reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;  in arm_smmu_init_context_bank()
747 	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));  in arm_smmu_init_context_bank()
753 		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;  in arm_smmu_init_context_bank()
757 		reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;  in arm_smmu_init_context_bank()
805 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_init_domain_context()  local
836 		cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;  in arm_smmu_init_domain_context()
851 		cfg->cbar = CBAR_TYPE_S2_TRANS;  in arm_smmu_init_domain_context()
870 	cfg->cbndx = ret;  in arm_smmu_init_domain_context()
872 		cfg->irptndx = atomic_inc_return(&smmu->irptndx);  in arm_smmu_init_domain_context()
873 		cfg->irptndx %= smmu->num_context_irqs;  in arm_smmu_init_domain_context()
875 		cfg->irptndx = cfg->cbndx;  in arm_smmu_init_domain_context()
903 	irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];  in arm_smmu_init_domain_context()
908 			cfg->irptndx, irq);  in arm_smmu_init_domain_context()
909 		cfg->irptndx = INVALID_IRPTNDX;  in arm_smmu_init_domain_context()
929 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_destroy_domain_context()  local
940 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_destroy_domain_context()
943 	if (cfg->irptndx != INVALID_IRPTNDX) {  in arm_smmu_destroy_domain_context()
944 		irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];  in arm_smmu_destroy_domain_context()
951 	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);  in arm_smmu_destroy_domain_context()
988 					  struct arm_smmu_master_cfg *cfg)  in arm_smmu_master_configure_smrs()  argument
997 	if (cfg->smrs)  in arm_smmu_master_configure_smrs()
1000 	smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);  in arm_smmu_master_configure_smrs()
1003 			cfg->num_streamids);  in arm_smmu_master_configure_smrs()
1008 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_master_configure_smrs()
1019 			.id	= cfg->streamids[i],  in arm_smmu_master_configure_smrs()
1024 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_master_configure_smrs()
1030 	cfg->smrs = smrs;  in arm_smmu_master_configure_smrs()
1041 				      struct arm_smmu_master_cfg *cfg)  in arm_smmu_master_free_smrs()  argument
1045 	struct arm_smmu_smr *smrs = cfg->smrs;  in arm_smmu_master_free_smrs()
1051 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_master_free_smrs()
1058 	cfg->smrs = NULL;  in arm_smmu_master_free_smrs()
1063 				      struct arm_smmu_master_cfg *cfg)  in arm_smmu_domain_add_master()  argument
1070 	ret = arm_smmu_master_configure_smrs(smmu, cfg);  in arm_smmu_domain_add_master()
1074 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_domain_add_master()
1077 		idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];  in arm_smmu_domain_add_master()
1079 		       (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);  in arm_smmu_domain_add_master()
1087 					  struct arm_smmu_master_cfg *cfg)  in arm_smmu_domain_remove_master()  argument
1094 	if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)  in arm_smmu_domain_remove_master()
1101 	for (i = 0; i < cfg->num_streamids; ++i) {  in arm_smmu_domain_remove_master()
1102 		u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];  in arm_smmu_domain_remove_master()
1108 	arm_smmu_master_free_smrs(smmu, cfg);  in arm_smmu_domain_remove_master()
1116 	struct arm_smmu_master_cfg *cfg;  in arm_smmu_attach_dev()  local
1146 	cfg = find_smmu_master_cfg(dev);  in arm_smmu_attach_dev()
1147 	if (!cfg)  in arm_smmu_attach_dev()
1150 	ret = arm_smmu_domain_add_master(smmu_domain, cfg);  in arm_smmu_attach_dev()
1159 	struct arm_smmu_master_cfg *cfg;  in arm_smmu_detach_dev()  local
1161 	cfg = find_smmu_master_cfg(dev);  in arm_smmu_detach_dev()
1162 	if (!cfg)  in arm_smmu_detach_dev()
1166 	arm_smmu_domain_remove_master(smmu_domain, cfg);  in arm_smmu_detach_dev()
1208 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in arm_smmu_iova_to_phys_hard()  local
1216 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_iova_to_phys_hard()
1301 	struct arm_smmu_master_cfg *cfg;  in arm_smmu_init_pci_device()  local
1305 	cfg = iommu_group_get_iommudata(group);  in arm_smmu_init_pci_device()
1306 	if (!cfg) {  in arm_smmu_init_pci_device()
1307 		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);  in arm_smmu_init_pci_device()
1308 		if (!cfg)  in arm_smmu_init_pci_device()
1311 		iommu_group_set_iommudata(group, cfg,  in arm_smmu_init_pci_device()
1315 	if (cfg->num_streamids >= MAX_MASTER_STREAMIDS)  in arm_smmu_init_pci_device()
1323 	for (i = 0; i < cfg->num_streamids; ++i)  in arm_smmu_init_pci_device()
1324 		if (cfg->streamids[i] == sid)  in arm_smmu_init_pci_device()
1328 	if (i == cfg->num_streamids)  in arm_smmu_init_pci_device()
1329 		cfg->streamids[cfg->num_streamids++] = sid;  in arm_smmu_init_pci_device()
1347 	iommu_group_set_iommudata(group, &master->cfg, NULL);  in arm_smmu_init_platform_device()