636 	void __iomem *cb_base;  in arm_smmu_context_fault()  local
638 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_context_fault()
639 	fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_context_fault()
649 	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);  in arm_smmu_context_fault()
652 	far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);  in arm_smmu_context_fault()
655 	far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);  in arm_smmu_context_fault()
671 	writel(fsr, cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_context_fault()
675 		writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);  in arm_smmu_context_fault()
712 	void __iomem *cb_base, *gr1_base;  in arm_smmu_init_context_bank()  local
716 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_init_context_bank()
754 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);  in arm_smmu_init_context_bank()
758 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);  in arm_smmu_init_context_bank()
761 		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);  in arm_smmu_init_context_bank()
767 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
771 			writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);  in arm_smmu_init_context_bank()
775 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);  in arm_smmu_init_context_bank()
781 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);  in arm_smmu_init_context_bank()
783 		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);  in arm_smmu_init_context_bank()
793 	writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_init_context_bank()
930 	void __iomem *cb_base;  in arm_smmu_destroy_domain_context()  local
940 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_destroy_domain_context()
941 	writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_destroy_domain_context()
1211 	void __iomem *cb_base;  in arm_smmu_iova_to_phys_hard()  local
1216 	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);  in arm_smmu_iova_to_phys_hard()
1221 		smmu_writeq(va, cb_base + ARM_SMMU_CB_ATS1PR);  in arm_smmu_iova_to_phys_hard()
1223 		writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);  in arm_smmu_iova_to_phys_hard()
1225 	if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,  in arm_smmu_iova_to_phys_hard()
1233 	phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);  in arm_smmu_iova_to_phys_hard()
1234 	phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;  in arm_smmu_iova_to_phys_hard()
1459 	void __iomem *cb_base;  in arm_smmu_device_reset()  local
1476 		cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);  in arm_smmu_device_reset()
1477 		writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);  in arm_smmu_device_reset()
1478 		writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);  in arm_smmu_device_reset()