937 				    struct arm_smmu_s1_cfg *cfg)  in arm_smmu_write_ctx_desc()  argument
945 	val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) |  in arm_smmu_write_ctx_desc()
950 	      CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT |  in arm_smmu_write_ctx_desc()
952 	cfg->cdptr[0] = cpu_to_le64(val);  in arm_smmu_write_ctx_desc()
954 	val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT;  in arm_smmu_write_ctx_desc()
955 	cfg->cdptr[1] = cpu_to_le64(val);  in arm_smmu_write_ctx_desc()
957 	cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT);  in arm_smmu_write_ctx_desc()
1018 		u64 cfg;  in arm_smmu_write_strtab_ent()  local
1020 		cfg = val & STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT;  in arm_smmu_write_strtab_ent()
1021 		switch (cfg) {  in arm_smmu_write_strtab_ent()
1116 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;  in arm_smmu_init_l2_strtab()  local
1117 	struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT];  in arm_smmu_init_l2_strtab()
1123 	strtab = &cfg->strtab[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS];  in arm_smmu_init_l2_strtab()
1429 		struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;  in arm_smmu_domain_free()  local
1431 		if (cfg->cdptr) {  in arm_smmu_domain_free()
1434 					  cfg->cdptr,  in arm_smmu_domain_free()
1435 					  cfg->cdptr_dma);  in arm_smmu_domain_free()
1437 			arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid);  in arm_smmu_domain_free()
1440 		struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;  in arm_smmu_domain_free()  local
1441 		if (cfg->vmid)  in arm_smmu_domain_free()
1442 			arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid);  in arm_smmu_domain_free()
1454 	struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;  in arm_smmu_domain_finalise_s1()  local
1460 	cfg->cdptr = dma_zalloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3,  in arm_smmu_domain_finalise_s1()
1461 					 &cfg->cdptr_dma, GFP_KERNEL);  in arm_smmu_domain_finalise_s1()
1462 	if (!cfg->cdptr) {  in arm_smmu_domain_finalise_s1()
1468 	cfg->cd.asid	= (u16)asid;  in arm_smmu_domain_finalise_s1()
1469 	cfg->cd.ttbr	= pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];  in arm_smmu_domain_finalise_s1()
1470 	cfg->cd.tcr	= pgtbl_cfg->arm_lpae_s1_cfg.tcr;  in arm_smmu_domain_finalise_s1()
1471 	cfg->cd.mair	= pgtbl_cfg->arm_lpae_s1_cfg.mair[0];  in arm_smmu_domain_finalise_s1()
1484 	struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;  in arm_smmu_domain_finalise_s2()  local
1490 	cfg->vmid	= (u16)vmid;  in arm_smmu_domain_finalise_s2()
1491 	cfg->vttbr	= pgtbl_cfg->arm_lpae_s2_cfg.vttbr;  in arm_smmu_domain_finalise_s2()
1492 	cfg->vtcr	= pgtbl_cfg->arm_lpae_s2_cfg.vtcr;  in arm_smmu_domain_finalise_s2()
1573 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;  in arm_smmu_get_step_for_sid()  local
1581 		l1_desc = &cfg->l1_desc[idx];  in arm_smmu_get_step_for_sid()
1586 		step = &cfg->strtab[sid * STRTAB_STE_DWORDS];  in arm_smmu_get_step_for_sid()
2017 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;  in arm_smmu_free_l2_strtab()  local
2020 	for (i = 0; i < cfg->num_l1_ents; ++i) {  in arm_smmu_free_l2_strtab()
2021 		struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[i];  in arm_smmu_free_l2_strtab()
2034 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;  in arm_smmu_init_l1_strtab()  local
2035 	size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_ents;  in arm_smmu_init_l1_strtab()
2038 	cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL);  in arm_smmu_init_l1_strtab()
2039 	if (!cfg->l1_desc) {  in arm_smmu_init_l1_strtab()
2044 	for (i = 0; i < cfg->num_l1_ents; ++i) {  in arm_smmu_init_l1_strtab()
2045 		arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]);  in arm_smmu_init_l1_strtab()
2058 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;  in arm_smmu_init_strtab_2lvl()  local
2071 	cfg->num_l1_ents = 1 << size;  in arm_smmu_init_strtab_2lvl()
2079 	l1size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);  in arm_smmu_init_strtab_2lvl()
2080 	strtab = dma_zalloc_coherent(smmu->dev, l1size, &cfg->strtab_dma,  in arm_smmu_init_strtab_2lvl()
2088 	cfg->strtab = strtab;  in arm_smmu_init_strtab_2lvl()
2096 	cfg->strtab_base_cfg = reg;  in arm_smmu_init_strtab_2lvl()
2103 				  cfg->strtab_dma);  in arm_smmu_init_strtab_2lvl()
2112 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;  in arm_smmu_init_strtab_linear()  local
2115 	strtab = dma_zalloc_coherent(smmu->dev, size, &cfg->strtab_dma,  in arm_smmu_init_strtab_linear()
2123 	cfg->strtab = strtab;  in arm_smmu_init_strtab_linear()
2124 	cfg->num_l1_ents = 1 << smmu->sid_bits;  in arm_smmu_init_strtab_linear()
2130 	cfg->strtab_base_cfg = reg;  in arm_smmu_init_strtab_linear()
2132 	arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents);  in arm_smmu_init_strtab_linear()
2162 	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;  in arm_smmu_free_strtab()  local
2163 	u32 size = cfg->num_l1_ents;  in arm_smmu_free_strtab()
2172 	dma_free_coherent(smmu->dev, size, cfg->strtab, cfg->strtab_dma);  in arm_smmu_free_strtab()
2221 	phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index];  in arm_smmu_write_msi_msg()  local
2226 	writeq_relaxed(doorbell, smmu->base + cfg[0]);  in arm_smmu_write_msi_msg()
2227 	writel_relaxed(msg->data, smmu->base + cfg[1]);  in arm_smmu_write_msi_msg()
2228 	writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);  in arm_smmu_write_msi_msg()