Lines Matching refs:iommu
231 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
251 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
255 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
256 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
260 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
262 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
263 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
264 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
267 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
271 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
272 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
276 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
278 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
279 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
295 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
297 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
298 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; in iommu_set_exclusion_range()
301 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
305 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
309 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
314 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
318 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
322 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
327 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
331 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
333 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
336 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
340 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
342 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
345 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
349 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
352 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
356 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
358 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
361 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
364 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
367 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
368 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
371 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
390 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
392 if (iommu->mmio_base) in iommu_unmap_mmio_space()
393 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
394 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
505 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
507 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_command_buffer()
510 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
517 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
519 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
521 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
522 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
524 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
531 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
535 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
537 entry = (u64)virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
540 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
543 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
546 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
548 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
552 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
554 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
557 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
560 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
564 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
566 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
568 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
572 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
573 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
575 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
578 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
580 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
584 static int __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
586 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
589 return iommu->ppr_log ? 0 : -ENOMEM; in alloc_ppr_log()
592 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
596 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
599 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
601 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
605 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
606 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
608 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); in iommu_enable_ppr_log()
609 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
612 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
614 if (iommu->ppr_log == NULL) in free_ppr_log()
617 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
620 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
622 if (!iommu_feature(iommu, FEATURE_GT)) in iommu_enable_gt()
625 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
658 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) in set_iommu_for_device() argument
660 amd_iommu_rlookup_table[devid] = iommu; in set_iommu_for_device()
667 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
687 set_iommu_for_device(iommu, devid); in set_dev_entry_from_acpi()
758 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; in set_device_exclusion_range() local
763 if (iommu) { in set_device_exclusion_range()
770 iommu->exclusion_start = m->range_start; in set_device_exclusion_range()
771 iommu->exclusion_length = m->range_length; in set_device_exclusion_range()
779 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
798 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
815 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
827 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
857 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
858 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
890 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
918 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
921 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
957 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
971 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
973 free_command_buffer(iommu); in free_iommu_one()
974 free_event_buffer(iommu); in free_iommu_one()
975 free_ppr_log(iommu); in free_iommu_one()
976 iommu_unmap_mmio_space(iommu); in free_iommu_one()
981 struct amd_iommu *iommu, *next; in free_iommu_all() local
983 for_each_iommu_safe(iommu, next) { in free_iommu_all()
984 list_del(&iommu->list); in free_iommu_all()
985 free_iommu_one(iommu); in free_iommu_all()
986 kfree(iommu); in free_iommu_all()
996 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1005 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1006 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1012 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1014 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1016 dev_name(&iommu->dev->dev)); in amd_iommu_erratum_746_workaround()
1019 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1028 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1038 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1044 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1047 dev_name(&iommu->dev->dev)); in amd_iommu_ats_write_check_workaround()
1055 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) in init_iommu_one() argument
1059 spin_lock_init(&iommu->lock); in init_iommu_one()
1062 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1063 iommu->index = amd_iommus_present++; in init_iommu_one()
1065 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1071 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1076 iommu->devid = h->devid; in init_iommu_one()
1077 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1078 iommu->pci_seg = h->pci_seg; in init_iommu_one()
1079 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1085 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1087 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1090 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1091 iommu->mmio_phys_end); in init_iommu_one()
1092 if (!iommu->mmio_base) in init_iommu_one()
1095 if (alloc_command_buffer(iommu)) in init_iommu_one()
1098 if (alloc_event_buffer(iommu)) in init_iommu_one()
1101 iommu->int_enabled = false; in init_iommu_one()
1103 ret = init_iommu_from_acpi(iommu, h); in init_iommu_one()
1107 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one()
1115 amd_iommu_rlookup_table[iommu->devid] = NULL; in init_iommu_one()
1128 struct amd_iommu *iommu; in init_iommu_all() local
1147 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1148 if (iommu == NULL) in init_iommu_all()
1151 ret = init_iommu_one(iommu, h); in init_iommu_all()
1167 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1171 if (!iommu_feature(iommu, FEATURE_PC)) in init_iommu_perf_ctr()
1177 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) || in init_iommu_perf_ctr()
1178 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) || in init_iommu_perf_ctr()
1187 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1188 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1189 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1196 struct amd_iommu *iommu = dev_get_drvdata(dev); in amd_iommu_show_cap() local
1197 return sprintf(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1205 struct amd_iommu *iommu = dev_get_drvdata(dev); in amd_iommu_show_features() local
1206 return sprintf(buf, "%llx\n", iommu->features); in amd_iommu_show_features()
1226 static int iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
1228 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
1231 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
1232 iommu->devid & 0xff); in iommu_init_pci()
1233 if (!iommu->dev) in iommu_init_pci()
1237 iommu->dev->match_driver = false; in iommu_init_pci()
1239 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
1240 &iommu->cap); in iommu_init_pci()
1241 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, in iommu_init_pci()
1243 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, in iommu_init_pci()
1246 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
1250 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); in iommu_init_pci()
1251 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); in iommu_init_pci()
1253 iommu->features = ((u64)high << 32) | low; in iommu_init_pci()
1255 if (iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
1260 pasmax = iommu->features & FEATURE_PASID_MASK; in iommu_init_pci()
1268 glxval = iommu->features & FEATURE_GLXVAL_MASK; in iommu_init_pci()
1277 if (iommu_feature(iommu, FEATURE_GT) && in iommu_init_pci()
1278 iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
1279 iommu->is_iommu_v2 = true; in iommu_init_pci()
1283 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) in iommu_init_pci()
1286 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) in iommu_init_pci()
1289 init_iommu_perf_ctr(iommu); in iommu_init_pci()
1291 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
1294 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number, in iommu_init_pci()
1302 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
1303 &iommu->stored_addr_lo); in iommu_init_pci()
1304 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
1305 &iommu->stored_addr_hi); in iommu_init_pci()
1308 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
1312 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
1315 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
1318 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
1319 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
1321 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu, in iommu_init_pci()
1323 iommu->index); in iommu_init_pci()
1325 return pci_enable_device(iommu->dev); in iommu_init_pci()
1334 struct amd_iommu *iommu; in print_iommu_info() local
1336 for_each_iommu(iommu) { in print_iommu_info()
1340 dev_name(&iommu->dev->dev), iommu->cap_ptr); in print_iommu_info()
1342 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { in print_iommu_info()
1345 if (iommu_feature(iommu, (1ULL << i))) in print_iommu_info()
1357 struct amd_iommu *iommu; in amd_iommu_init_pci() local
1360 for_each_iommu(iommu) { in amd_iommu_init_pci()
1361 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
1368 for_each_iommu(iommu) in amd_iommu_init_pci()
1369 iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
1388 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
1392 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
1396 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
1400 iommu); in iommu_setup_msi()
1403 pci_disable_msi(iommu->dev); in iommu_setup_msi()
1407 iommu->int_enabled = true; in iommu_setup_msi()
1412 static int iommu_init_msi(struct amd_iommu *iommu) in iommu_init_msi() argument
1416 if (iommu->int_enabled) in iommu_init_msi()
1419 if (iommu->dev->msi_cap) in iommu_init_msi()
1420 ret = iommu_setup_msi(iommu); in iommu_init_msi()
1428 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_msi()
1430 if (iommu->ppr_log != NULL) in iommu_init_msi()
1431 iommu_feature_enable(iommu, CONTROL_PPFINT_EN); in iommu_init_msi()
1580 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
1582 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
1583 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
1584 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
1586 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
1587 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
1588 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
1590 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
1591 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
1592 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
1594 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
1595 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
1596 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
1601 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
1604 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
1607 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
1611 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
1614 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
1631 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
1632 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
1633 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
1634 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
1639 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
1643 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
1646 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
1647 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
1656 struct amd_iommu *iommu; in early_enable_iommus() local
1658 for_each_iommu(iommu) { in early_enable_iommus()
1659 iommu_disable(iommu); in early_enable_iommus()
1660 iommu_init_flags(iommu); in early_enable_iommus()
1661 iommu_set_device_table(iommu); in early_enable_iommus()
1662 iommu_enable_command_buffer(iommu); in early_enable_iommus()
1663 iommu_enable_event_buffer(iommu); in early_enable_iommus()
1664 iommu_set_exclusion_range(iommu); in early_enable_iommus()
1665 iommu_enable(iommu); in early_enable_iommus()
1666 iommu_flush_all_caches(iommu); in early_enable_iommus()
1672 struct amd_iommu *iommu; in enable_iommus_v2() local
1674 for_each_iommu(iommu) { in enable_iommus_v2()
1675 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
1676 iommu_enable_gt(iommu); in enable_iommus_v2()
1689 struct amd_iommu *iommu; in disable_iommus() local
1691 for_each_iommu(iommu) in disable_iommus()
1692 iommu_disable(iommu); in disable_iommus()
1702 struct amd_iommu *iommu; in amd_iommu_resume() local
1704 for_each_iommu(iommu) in amd_iommu_resume()
1705 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
1963 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
1966 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
1967 ret = iommu_init_msi(iommu); in amd_iommu_enable_interrupts()
2135 struct amd_iommu *iommu; in amd_iommu_init() local
2138 for_each_iommu(iommu) in amd_iommu_init()
2139 iommu_flush_all_caches(iommu); in amd_iommu_init()
2169 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
2287 struct amd_iommu *iommu; in amd_iommu_pc_get_max_banks() local
2291 iommu = amd_iommu_rlookup_table[devid]; in amd_iommu_pc_get_max_banks()
2292 if (iommu) in amd_iommu_pc_get_max_banks()
2293 ret = iommu->max_banks; in amd_iommu_pc_get_max_banks()
2307 struct amd_iommu *iommu; in amd_iommu_pc_get_max_counters() local
2311 iommu = amd_iommu_rlookup_table[devid]; in amd_iommu_pc_get_max_counters()
2312 if (iommu) in amd_iommu_pc_get_max_counters()
2313 ret = iommu->max_counters; in amd_iommu_pc_get_max_counters()
2319 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu, in iommu_pc_get_set_reg_val() argument
2333 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) | in iommu_pc_get_set_reg_val()
2334 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg_val()
2340 writel((u32)*value, iommu->mmio_base + offset); in iommu_pc_get_set_reg_val()
2341 writel((*value >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg_val()
2343 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg_val()
2345 *value = readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg_val()
2355 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; in amd_iommu_pc_get_set_reg_val() local
2358 if (!amd_iommu_pc_present || iommu == NULL) in amd_iommu_pc_get_set_reg_val()
2361 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn, in amd_iommu_pc_get_set_reg_val()