620 	fault.pasid     = PPR_PASID(raw[0]);  in iommu_handle_ppr_entry()
841 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,  in build_inv_iommu_pasid()  argument
848 	cmd->data[0]  = pasid;  in build_inv_iommu_pasid()
859 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,  in build_inv_iotlb_pasid()  argument
867 	cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;  in build_inv_iotlb_pasid()
870 	cmd->data[1] |= (pasid & 0xff) << 16;  in build_inv_iotlb_pasid()
879 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,  in build_complete_ppr()  argument
886 		cmd->data[1]  = pasid;  in build_complete_ppr()
3267 static int __flush_pasid(struct protection_domain *domain, int pasid,  in __flush_pasid()  argument
3277 	build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);  in __flush_pasid()
3310 		build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,  in __flush_pasid()
3328 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,  in __amd_iommu_flush_page()  argument
3333 	return __flush_pasid(domain, pasid, address, false);  in __amd_iommu_flush_page()
3336 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,  in amd_iommu_flush_page()  argument
3344 	ret = __amd_iommu_flush_page(domain, pasid, address);  in amd_iommu_flush_page()
3351 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)  in __amd_iommu_flush_tlb()  argument
3355 	return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,  in __amd_iommu_flush_tlb()
3359 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)  in amd_iommu_flush_tlb()  argument
3366 	ret = __amd_iommu_flush_tlb(domain, pasid);  in amd_iommu_flush_tlb()
3373 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)  in __get_gcr3_pte()  argument
3380 		index = (pasid >> (9 * level)) & 0x1ff;  in __get_gcr3_pte()
3405 static int __set_gcr3(struct protection_domain *domain, int pasid,  in __set_gcr3()  argument
3413 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);  in __set_gcr3()
3419 	return __amd_iommu_flush_tlb(domain, pasid);  in __set_gcr3()
3422 static int __clear_gcr3(struct protection_domain *domain, int pasid)  in __clear_gcr3()  argument
3429 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);  in __clear_gcr3()
3435 	return __amd_iommu_flush_tlb(domain, pasid);  in __clear_gcr3()
3438 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,  in amd_iommu_domain_set_gcr3()  argument
3446 	ret = __set_gcr3(domain, pasid, cr3);  in amd_iommu_domain_set_gcr3()
3453 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)  in amd_iommu_domain_clear_gcr3()  argument
3460 	ret = __clear_gcr3(domain, pasid);  in amd_iommu_domain_clear_gcr3()
3467 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,  in amd_iommu_complete_ppr()  argument
3479 	build_complete_ppr(&cmd, dev_data->devid, pasid, status,  in amd_iommu_complete_ppr()