141 	dd->pcidev = pdev;  in qib_pcie_ddinit()
190 	pci_disable_device(dd->pcidev);  in qib_pcie_ddcleanup()
191 	pci_release_regions(dd->pcidev);  in qib_pcie_ddcleanup()
193 	pci_set_drvdata(dd->pcidev, NULL);  in qib_pcie_ddcleanup()
204 	ret = pci_msix_vec_count(dd->pcidev);  in qib_msix_setup()
220 	ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec);  in qib_msix_setup()
242 	qib_enable_intx(dd->pcidev);  in qib_msix_setup()
252 	struct pci_dev *pdev = dd->pcidev;  in qib_msi_setup()
281 	if (!pci_is_pcie(dd->pcidev)) {  in qib_pcie_params()
289 	pos = dd->pcidev->msix_cap;  in qib_pcie_params()
294 		pos = dd->pcidev->msi_cap;  in qib_pcie_params()
301 		qib_enable_intx(dd->pcidev);  in qib_pcie_params()
303 	pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);  in qib_pcie_params()
363 	pos = dd->pcidev->msi_cap;  in qib_reinit_intr()
371 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,  in qib_reinit_intr()
373 	pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,  in qib_reinit_intr()
375 	pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);  in qib_reinit_intr()
378 		pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,  in qib_reinit_intr()
382 	pci_write_config_word(dd->pcidev, pos +  in qib_reinit_intr()
388 		qib_enable_intx(dd->pcidev);  in qib_reinit_intr()
393 	pci_set_master(dd->pcidev);  in qib_reinit_intr()
406 	pci_disable_msi(dd->pcidev);  in qib_nomsi()
414 	pci_disable_msix(dd->pcidev);  in qib_nomsix()
456 	pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);  in qib_pcie_getcmd()
457 	pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);  in qib_pcie_getcmd()
458 	pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);  in qib_pcie_getcmd()
465 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,  in qib_pcie_reenable()
469 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,  in qib_pcie_reenable()
474 	pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);  in qib_pcie_reenable()
475 	pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);  in qib_pcie_reenable()
476 	pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);  in qib_pcie_reenable()
477 	r = pci_enable_device(dd->pcidev);  in qib_pcie_reenable()
505 	parent = dd->pcidev->bus->self;  in qib_tune_pcie_coalesce()
507 		qib_devinfo(dd->pcidev, "Parent not root\n");  in qib_tune_pcie_coalesce()
569 	parent = dd->pcidev->bus->self;  in qib_tune_pcie_caps()
571 		qib_devinfo(dd->pcidev, "Parent not root\n");  in qib_tune_pcie_caps()
575 	if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))  in qib_tune_pcie_caps()
581 	ep_mpss = dd->pcidev->pcie_mpss;  in qib_tune_pcie_caps()
582 	ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;  in qib_tune_pcie_caps()
599 		pcie_set_mps(dd->pcidev, 128 << ep_mps);  in qib_tune_pcie_caps()
613 	ep_mrrs = pcie_get_readrq(dd->pcidev);  in qib_tune_pcie_caps()
621 		pcie_set_readrq(dd->pcidev, ep_mrrs);  in qib_tune_pcie_caps()