Lines Matching refs:ctxt
776 enum qib_ureg regno, int ctxt) in qib_read_ureg32() argument
781 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg32()
797 enum qib_ureg regno, int ctxt) in qib_read_ureg() argument
803 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg()
818 enum qib_ureg regno, u64 value, int ctxt) in qib_write_ureg() argument
825 dd->ureg_align * ctxt); in qib_write_ureg()
830 dd->ureg_align * ctxt); in qib_write_ureg()
887 const u16 regno, unsigned ctxt, in qib_write_kreg_ctxt() argument
890 qib_write_kreg(dd, regno + ctxt, value); in qib_write_kreg_ctxt()
2712 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { in qib_update_rhdrq_dca()
2715 cspec->rhdr_cpu[rcd->ctxt] = cpu; in qib_update_rhdrq_dca()
2716 rmp = &dca_rcvhdr_reg_map[rcd->ctxt]; in qib_update_rhdrq_dca()
2721 "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu, in qib_update_rhdrq_dca()
3065 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; in adjust_rcv_timeout()
3078 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; in adjust_rcv_timeout()
3079 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); in adjust_rcv_timeout()
3201 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); in qib_7322pintr()
3502 unsigned ctxt; in qib_setup_7322_interrupt() local
3504 ctxt = i - ARRAY_SIZE(irq_table); in qib_setup_7322_interrupt()
3506 arg = dd->rcd[ctxt]; in qib_setup_7322_interrupt()
3509 if (qib_krcvq01_no_msi && ctxt < 2) in qib_setup_7322_interrupt()
3514 lsb = QIB_I_RCVAVAIL_LSB + ctxt; in qib_setup_7322_interrupt()
3861 u32 ctxt; in qib_7322_clear_tids() local
3867 ctxt = rcd->ctxt; in qib_7322_clear_tids()
3873 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); in qib_7322_clear_tids()
4491 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); in qib_update_7322_usrhead()
4493 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4494 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4502 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); in qib_7322_hdrqempty()
4506 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); in qib_7322_hdrqempty()
4534 int ctxt) in rcvctrl_7322_mod() argument
4555 if (ctxt < 0) { in rcvctrl_7322_mod()
4559 mask = (1ULL << ctxt); in rcvctrl_7322_mod()
4560 rcd = dd->rcd[ctxt]; in rcvctrl_7322_mod()
4570 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, in rcvctrl_7322_mod()
4572 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, in rcvctrl_7322_mod()
4596 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { in rcvctrl_7322_mod()
4603 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); in rcvctrl_7322_mod()
4604 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); in rcvctrl_7322_mod()
4608 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); in rcvctrl_7322_mod()
4609 dd->rcd[ctxt]->head = val; in rcvctrl_7322_mod()
4611 if (ctxt < dd->first_user_ctxt) in rcvctrl_7322_mod()
4613 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_7322_mod()
4615 dd->rcd[ctxt] && dd->rhdrhead_intr_off) { in rcvctrl_7322_mod()
4617 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; in rcvctrl_7322_mod()
4618 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_7322_mod()
4624 if (ctxt >= 0) { in rcvctrl_7322_mod()
4625 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0); in rcvctrl_7322_mod()
4626 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0); in rcvctrl_7322_mod()
4629 TIDFLOW_ERRBITS, ctxt); in rcvctrl_7322_mod()
6375 unsigned ctxt; in write_7322_initregs() local
6378 ctxt = (i % n) * dd->num_pports + pidx; in write_7322_initregs()
6380 ctxt = (i % n) + 1; in write_7322_initregs()
6382 ctxt = ppd->hw_pidx; in write_7322_initregs()
6383 val |= ctxt << (5 * (i % 6)); in write_7322_initregs()
7073 if (rcd->ctxt < NUM_IB_PORTS) { in qib_7322_init_ctxt()
7076 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0; in qib_7322_init_ctxt()
7084 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt; in qib_7322_init_ctxt()