729 struct qib_devdata {  struct
730 	struct qib_ibdev verbs_dev;     /* must be first */
731 	struct list_head list;
734 	struct pci_dev *pcidev;
735 	struct cdev *user_cdev;
736 	struct cdev *diag_cdev;
737 	struct device *user_device;
738 	struct device *diag_device;
741 	u64 __iomem *kregbase;
743 	u64 __iomem *kregend;
745 	resource_size_t physaddr;
747 	struct qib_ctxtdata **rcd; /* Receive Context Data */
752 	struct qib_pportdata *pport;
753 	struct qib_chip_specific *cspec; /* chip-specific */
756 	void __iomem *pio2kbase;
781 	int (*f_intr_fallback)(struct qib_devdata *);  argument
783 	int (*f_reset)(struct qib_devdata *);  argument
786 	int (*f_early_init)(struct qib_devdata *);  argument
787 	void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);  argument
788 	void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,  argument
790 	void (*f_cleanup)(struct qib_devdata *);  argument
795 	void (*f_free_irq)(struct qib_devdata *);  argument
797 					(struct qib_devdata *, __le32 *);  argument
798 	void (*f_config_ctxts)(struct qib_devdata *);  argument
811 	int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,  argument
814 	int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);  argument
825 	void (*f_set_intr_state)(struct qib_devdata *, u32);  argument
826 	void (*f_set_armlaunch)(struct qib_devdata *, u32);  argument
827 	void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);  argument
828 	int (*f_late_initreg)(struct qib_devdata *);  argument
842 	u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,  argument
844 	u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,  argument
847 	void (*f_initvl15_bufs)(struct qib_devdata *);  argument
849 	void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,  argument
851 	void (*f_writescratch)(struct qib_devdata *, u32);  argument
852 	int (*f_tempsense_rd)(struct qib_devdata *, int regnum);  argument
854 	int (*f_notify_dca)(struct qib_devdata *, unsigned long event);  argument
857 	char *boardname; /* human readable board info */
860 	u64 tidtemplate;
862 	u64 tidinvalid;
865 	u32 pioavregs;
867 	u32 flags;
869 	u32 lastctxt_piobuf;
872 	u64 z_int_counter;
874 	u64 __percpu *int_counter;
877 	u32 pbufsctxt;
879 	u32 ctxts_extrabuf;
884 	u32 cfgctxts;
888 	u32 freectxts;
894 	u32 upd_pio_shadow;
897 	u32 maxpkts_call;
898 	u32 avgpkts_call;
899 	u64 nopiobufs;
902 	u16 vendorid;
904 	u16 deviceid;
906 	int wc_cookie;
907 	unsigned long wc_base;
908 	unsigned long wc_len;
911 	struct page **pageshadow;
913 	dma_addr_t *physshadow;
914 	u64 __iomem *egrtidbase;
915 	spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */
917 	spinlock_t uctxt_lock; /* rcd and user context changes */
923 	u64 *devstatusp;
924 	char *freezemsg; /* freeze msg if hw error put chip in freeze */
925 	u32 freezelen; /* max length of freezemsg */
927 	struct timer_list stats_timer;
930 	struct timer_list intrchk_timer;
931 	unsigned long ureg_align; /* user register alignment */
937 	spinlock_t pioavail_lock;
941 	u32 last_pio;
945 	u32 min_kernel_pio;
961 	unsigned long pioavailshadow[6];
963 	unsigned long pioavailkernel[6];
965 	unsigned long pio_need_disarm[3];
967 	unsigned long pio_writing[3];
969 	u64 revision;
971 	__be64 base_guid;
977 	u64 piobufbase;
978 	u32 pio2k_bufbase;
983 	u32 nguid;
988 	unsigned long rcvctrl; /* shadow per device rcvctrl */
989 	unsigned long sendctrl; /* shadow per device sendctrl */
992 	u32 rcvhdrcnt;
994 	u32 rcvhdrsize;
996 	u32 rcvhdrentsize;
998 	u32 ctxtcnt;
1000 	u32 palign;
1002 	u32 piobcnt2k;
1004 	u32 piosize2k;
1006 	u32 piosize2kmax_dwords;
1008 	u32 piobcnt4k;
1010 	u32 piosize4k;
1012 	u32 rcvegrbase;
1014 	u32 rcvtidbase;
1016 	u32 rcvtidcnt;
1018 	u32 uregbase;
1020 	u32 control;
1023 	u32 align4k;
1025 	u16 rcvegrbufsize;
1027 	u16 rcvegrbufsize_shift;
1029 	u32 lbus_width;
1031 	u32 lbus_speed;
1032 	int unit; /* unit # of this chip */
1036 	u32 msi_lo;
1038 	u32 msi_hi;
1040 	u16 msi_data;
1042 	u32 pcibar0;
1044 	u32 pcibar1;
1045 	u64 rhdrhead_intr_off;
1051 	u8 serial[16];
1053 	u8 boardversion[96];
1054 	u8 lbus_info[32]; /* human readable localbus info */
1056 	u8 majrev;
1058 	u8 minrev;
1062 	u8 num_pports;
1064 	u8 first_user_ctxt;
1065 	u8 n_krcv_queues;
1066 	u8 qpn_mask;
1067 	u8 skip_kctxt_mask;
1069 	u16 rhf_offset; /* offset of RHF within receive header entry */
1074 	u8 gpio_sda_num;
1075 	u8 gpio_scl_num;
1076 	u8 twsi_eeprom_dev;
1077 	u8 board_atten;
1081 	spinlock_t eep_st_lock;
1083 	struct mutex eep_lock;
1084 	uint64_t traffic_wds;
1089 	struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1090 	struct qib_diag_client *diag_client;
1091 	spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1092 	struct diag_observer_list_elt *diag_observer_list;
1094 	u8 psxmitwait_supported;
1096 	u16 psxmitwait_check_rate;
1098 	struct tasklet_struct error_tasklet;
1100 	struct kthread_worker *worker;
1102 	int assigned_node_id; /* NUMA node closest to HCA */