Lines Matching refs:st
68 static int adf4350_sync_config(struct adf4350_state *st) in adf4350_sync_config() argument
73 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
82 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
83 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
86 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
87 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
88 i, (u32)st->regs[i] | i); in adf4350_sync_config()
98 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_reg_access() local
106 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); in adf4350_reg_access()
107 ret = adf4350_sync_config(st); in adf4350_reg_access()
109 *readval = st->regs_hw[reg]; in adf4350_reg_access()
117 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) in adf4350_tune_r_cnt() argument
119 struct adf4350_platform_data *pdata = st->pdata; in adf4350_tune_r_cnt()
123 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / in adf4350_tune_r_cnt()
125 } while (st->fpfd > ADF4350_MAX_FREQ_PFD); in adf4350_tune_r_cnt()
130 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) in adf4350_set_freq() argument
132 struct adf4350_platform_data *pdata = st->pdata; in adf4350_set_freq()
138 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) in adf4350_set_freq()
149 st->r4_rf_div_sel = 0; in adf4350_set_freq()
153 st->r4_rf_div_sel++; in adf4350_set_freq()
163 chspc = st->chspc; in adf4350_set_freq()
168 r_cnt = adf4350_tune_r_cnt(st, r_cnt); in adf4350_set_freq()
169 st->r1_mod = st->fpfd / chspc; in adf4350_set_freq()
175 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); in adf4350_set_freq()
178 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); in adf4350_set_freq()
179 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ in adf4350_set_freq()
180 st->r0_fract = do_div(tmp, st->r1_mod); in adf4350_set_freq()
181 st->r0_int = tmp; in adf4350_set_freq()
182 } while (mdiv > st->r0_int); in adf4350_set_freq()
184 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); in adf4350_set_freq()
186 if (st->r0_fract && st->r1_mod) { in adf4350_set_freq()
187 div_gcd = gcd(st->r1_mod, st->r0_fract); in adf4350_set_freq()
188 st->r1_mod /= div_gcd; in adf4350_set_freq()
189 st->r0_fract /= div_gcd; in adf4350_set_freq()
191 st->r0_fract = 0; in adf4350_set_freq()
192 st->r1_mod = 1; in adf4350_set_freq()
195 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" in adf4350_set_freq()
198 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, in adf4350_set_freq()
199 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", in adf4350_set_freq()
202 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | in adf4350_set_freq()
203 ADF4350_REG0_FRACT(st->r0_fract); in adf4350_set_freq()
205 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | in adf4350_set_freq()
206 ADF4350_REG1_MOD(st->r1_mod) | in adf4350_set_freq()
209 st->regs[ADF4350_REG2] = in adf4350_set_freq()
219 st->regs[ADF4350_REG3] = pdata->r3_user_settings & in adf4350_set_freq()
227 st->regs[ADF4350_REG4] = in adf4350_set_freq()
229 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | in adf4350_set_freq()
239 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; in adf4350_set_freq()
240 st->freq_req = freq; in adf4350_set_freq()
242 return adf4350_sync_config(st); in adf4350_set_freq()
250 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_write() local
262 ret = adf4350_set_freq(st, readin); in adf4350_write()
270 if (st->clk) { in adf4350_write()
271 tmp = clk_round_rate(st->clk, readin); in adf4350_write()
276 ret = clk_set_rate(st->clk, tmp); in adf4350_write()
280 st->clkin = readin; in adf4350_write()
281 ret = adf4350_set_freq(st, st->freq_req); in adf4350_write()
287 st->chspc = readin; in adf4350_write()
291 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; in adf4350_write()
293 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; in adf4350_write()
295 adf4350_sync_config(st); in adf4350_write()
310 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_read() local
317 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * in adf4350_read()
318 (u64)st->fpfd; in adf4350_read()
319 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); in adf4350_read()
321 if (gpio_is_valid(st->pdata->gpio_lock_detect)) in adf4350_read()
322 if (!gpio_get_value(st->pdata->gpio_lock_detect)) { in adf4350_read()
323 dev_dbg(&st->spi->dev, "PLL un-locked\n"); in adf4350_read()
328 if (st->clk) in adf4350_read()
329 st->clkin = clk_get_rate(st->clk); in adf4350_read()
331 val = st->clkin; in adf4350_read()
334 val = st->chspc; in adf4350_read()
337 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); in adf4350_read()
498 struct adf4350_state *st; in adf4350_probe() local
525 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in adf4350_probe()
531 st = iio_priv(indio_dev); in adf4350_probe()
533 st->reg = devm_regulator_get(&spi->dev, "vcc"); in adf4350_probe()
534 if (!IS_ERR(st->reg)) { in adf4350_probe()
535 ret = regulator_enable(st->reg); in adf4350_probe()
541 st->spi = spi; in adf4350_probe()
542 st->pdata = pdata; in adf4350_probe()
553 st->chspc = pdata->channel_spacing; in adf4350_probe()
555 st->clk = clk; in adf4350_probe()
556 st->clkin = clk_get_rate(clk); in adf4350_probe()
558 st->clkin = pdata->clkin; in adf4350_probe()
561 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? in adf4350_probe()
564 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); in adf4350_probe()
578 ret = adf4350_set_freq(st, pdata->power_up_frequency); in adf4350_probe()
590 if (!IS_ERR(st->reg)) in adf4350_probe()
591 regulator_disable(st->reg); in adf4350_probe()
602 struct adf4350_state *st = iio_priv(indio_dev); in adf4350_remove() local
603 struct regulator *reg = st->reg; in adf4350_remove()
605 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; in adf4350_remove()
606 adf4350_sync_config(st); in adf4350_remove()
610 if (st->clk) in adf4350_remove()
611 clk_disable_unprepare(st->clk); in adf4350_remove()