106 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,  in xadc_write_reg()  argument
109 	writel(val, xadc->base + reg);  in xadc_write_reg()
112 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,  in xadc_read_reg()  argument
115 	*val = readl(xadc->base + reg);  in xadc_read_reg()
128 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,  in xadc_zynq_write_fifo()  argument
134 		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);  in xadc_zynq_write_fifo()
137 static void xadc_zynq_drain_fifo(struct xadc *xadc)  in xadc_zynq_drain_fifo()  argument
141 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
144 		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_drain_fifo()
145 		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
149 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,  in xadc_zynq_update_intmsk()  argument
152 	xadc->zynq_intmask &= ~mask;  in xadc_zynq_update_intmsk()
153 	xadc->zynq_intmask |= val;  in xadc_zynq_update_intmsk()
155 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,  in xadc_zynq_update_intmsk()
156 		xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_update_intmsk()
159 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_write_adc_reg()  argument
166 	spin_lock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
167 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_write_adc_reg()
170 	reinit_completion(&xadc->completion);  in xadc_zynq_write_adc_reg()
173 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_write_adc_reg()
174 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_write_adc_reg()
177 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_write_adc_reg()
179 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_write_adc_reg()
180 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
182 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_write_adc_reg()
188 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_write_adc_reg()
193 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_read_adc_reg()  argument
203 	spin_lock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
204 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_read_adc_reg()
206 	xadc_zynq_drain_fifo(xadc);  in xadc_zynq_read_adc_reg()
207 	reinit_completion(&xadc->completion);  in xadc_zynq_read_adc_reg()
209 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_read_adc_reg()
210 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_read_adc_reg()
213 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_read_adc_reg()
215 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_read_adc_reg()
216 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
217 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_read_adc_reg()
223 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
224 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
248 	struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);  in xadc_zynq_unmask_worker()  local
251 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);  in xadc_zynq_unmask_worker()
255 	spin_lock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
258 	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;  in xadc_zynq_unmask_worker()
259 	xadc->zynq_masked_alarm &= misc_sts;  in xadc_zynq_unmask_worker()
262 	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;  in xadc_zynq_unmask_worker()
265 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);  in xadc_zynq_unmask_worker()
267 	xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_unmask_worker()
269 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
272 	if (xadc->zynq_masked_alarm) {  in xadc_zynq_unmask_worker()
273 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_unmask_worker()
282 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_interrupt_handler()  local
285 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_interrupt_handler()
287 	status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_interrupt_handler()
292 	spin_lock(&xadc->lock);  in xadc_zynq_interrupt_handler()
294 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);  in xadc_zynq_interrupt_handler()
297 		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_interrupt_handler()
299 		complete(&xadc->completion);  in xadc_zynq_interrupt_handler()
304 		xadc->zynq_masked_alarm |= status;  in xadc_zynq_interrupt_handler()
309 		xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_interrupt_handler()
315 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_interrupt_handler()
318 	spin_unlock(&xadc->lock);  in xadc_zynq_interrupt_handler()
329 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_setup()  local
340 	xadc->zynq_intmask = ~0;  in xadc_zynq_setup()
342 	pcap_rate = clk_get_rate(xadc->clk);  in xadc_zynq_setup()
363 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);  in xadc_zynq_setup()
364 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);  in xadc_zynq_setup()
365 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);  in xadc_zynq_setup()
366 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);  in xadc_zynq_setup()
367 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |  in xadc_zynq_setup()
374 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)  in xadc_zynq_get_dclk_rate()  argument
379 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);  in xadc_zynq_get_dclk_rate()
396 	return clk_get_rate(xadc->clk) / div;  in xadc_zynq_get_dclk_rate()
399 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_zynq_update_alarm()  argument
407 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_zynq_update_alarm()
410 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_update_alarm()
411 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);  in xadc_zynq_update_alarm()
413 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,  in xadc_zynq_update_alarm()
416 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_zynq_update_alarm()
428 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_read_adc_reg()  argument
433 	xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32);  in xadc_axi_read_adc_reg()
439 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_write_adc_reg()  argument
442 	xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val);  in xadc_axi_write_adc_reg()
450 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_setup()  local
452 	xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);  in xadc_axi_setup()
453 	xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);  in xadc_axi_setup()
461 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_interrupt_handler()  local
465 	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);  in xadc_axi_interrupt_handler()
466 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);  in xadc_axi_interrupt_handler()
472 	if ((status & XADC_AXI_INT_EOS) && xadc->trigger)  in xadc_axi_interrupt_handler()
473 		iio_trigger_poll(xadc->trigger);  in xadc_axi_interrupt_handler()
488 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);  in xadc_axi_interrupt_handler()
493 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_axi_update_alarm()  argument
507 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_axi_update_alarm()
508 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_axi_update_alarm()
511 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_axi_update_alarm()
512 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_axi_update_alarm()
515 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)  in xadc_axi_get_dclk()  argument
517 	return clk_get_rate(xadc->clk);  in xadc_axi_get_dclk()
530 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in _xadc_update_adc_reg()  argument
536 	ret = _xadc_read_adc_reg(xadc, reg, &tmp);  in _xadc_update_adc_reg()
540 	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);  in _xadc_update_adc_reg()
543 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_update_adc_reg()  argument
548 	mutex_lock(&xadc->mutex);  in xadc_update_adc_reg()
549 	ret = _xadc_update_adc_reg(xadc, reg, mask, val);  in xadc_update_adc_reg()
550 	mutex_unlock(&xadc->mutex);  in xadc_update_adc_reg()
555 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)  in xadc_get_dclk_rate()  argument
557 	return xadc->ops->get_dclk_rate(xadc);  in xadc_get_dclk_rate()
563 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_update_scan_mode()  local
568 	kfree(xadc->data);  in xadc_update_scan_mode()
569 	xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL);  in xadc_update_scan_mode()
570 	if (!xadc->data)  in xadc_update_scan_mode()
608 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_trigger_handler()  local
612 	if (!xadc->data)  in xadc_trigger_handler()
619 		xadc_read_adc_reg(xadc, chan, &xadc->data[j]);  in xadc_trigger_handler()
623 	iio_push_to_buffers(indio_dev, xadc->data);  in xadc_trigger_handler()
633 	struct xadc *xadc = iio_trigger_get_drvdata(trigger);  in xadc_trigger_set_state()  local
639 	mutex_lock(&xadc->mutex);  in xadc_trigger_set_state()
643 		if (xadc->trigger != NULL) {  in xadc_trigger_set_state()
647 			xadc->trigger = trigger;  in xadc_trigger_set_state()
648 			if (trigger == xadc->convst_trigger)  in xadc_trigger_set_state()
653 		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,  in xadc_trigger_set_state()
658 		xadc->trigger = NULL;  in xadc_trigger_set_state()
661 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_trigger_set_state()
662 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_trigger_set_state()
663 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS);  in xadc_trigger_set_state()
668 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_trigger_set_state()
669 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_trigger_set_state()
672 	mutex_unlock(&xadc->mutex);  in xadc_trigger_set_state()
708 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)  in xadc_power_adc_b()  argument
722 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,  in xadc_power_adc_b()
726 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)  in xadc_get_seq_mode()  argument
730 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)  in xadc_get_seq_mode()
742 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_postdisable()  local
752 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_postdisable()
756 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_postdisable()
760 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_postdisable()
765 	return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);  in xadc_postdisable()
770 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_preenable()  local
775 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
781 	seq_mode = xadc_get_seq_mode(xadc, scan_mask);  in xadc_preenable()
783 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_preenable()
787 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_preenable()
791 	ret = xadc_power_adc_b(xadc, seq_mode);  in xadc_preenable()
795 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
816 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_read_raw()  local
825 		ret = xadc_read_adc_reg(xadc, chan->address, &val16);  in xadc_read_raw()
870 		ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);  in xadc_read_raw()
878 		*val = xadc_get_dclk_rate(xadc) / div / 26;  in xadc_read_raw()
889 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_write_raw()  local
890 	unsigned long clk_rate = xadc_get_dclk_rate(xadc);  in xadc_write_raw()
921 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,  in xadc_write_raw()
1044 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_parse_dt()  local
1057 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;  in xadc_parse_dt()
1059 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;  in xadc_parse_dt()
1061 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;  in xadc_parse_dt()
1065 	if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {  in xadc_parse_dt()
1071 		if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {  in xadc_parse_dt()
1140 	struct xadc *xadc;  in xadc_probe()  local
1156 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc));  in xadc_probe()
1160 	xadc = iio_priv(indio_dev);  in xadc_probe()
1161 	xadc->ops = id->data;  in xadc_probe()
1162 	init_completion(&xadc->completion);  in xadc_probe()
1163 	mutex_init(&xadc->mutex);  in xadc_probe()
1164 	spin_lock_init(&xadc->lock);  in xadc_probe()
1165 	INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);  in xadc_probe()
1168 	xadc->base = devm_ioremap_resource(&pdev->dev, mem);  in xadc_probe()
1169 	if (IS_ERR(xadc->base))  in xadc_probe()
1170 		return PTR_ERR(xadc->base);  in xadc_probe()
1182 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1189 		xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");  in xadc_probe()
1190 		if (IS_ERR(xadc->convst_trigger)) {  in xadc_probe()
1191 			ret = PTR_ERR(xadc->convst_trigger);  in xadc_probe()
1194 		xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,  in xadc_probe()
1196 		if (IS_ERR(xadc->samplerate_trigger)) {  in xadc_probe()
1197 			ret = PTR_ERR(xadc->samplerate_trigger);  in xadc_probe()
1202 	xadc->clk = devm_clk_get(&pdev->dev, NULL);  in xadc_probe()
1203 	if (IS_ERR(xadc->clk)) {  in xadc_probe()
1204 		ret = PTR_ERR(xadc->clk);  in xadc_probe()
1207 	clk_prepare_enable(xadc->clk);  in xadc_probe()
1209 	ret = xadc->ops->setup(pdev, indio_dev, irq);  in xadc_probe()
1213 	ret = request_irq(irq, xadc->ops->interrupt_handler, 0,  in xadc_probe()
1219 		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1220 			&xadc->threshold[i]);  in xadc_probe()
1222 	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);  in xadc_probe()
1232 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);  in xadc_probe()
1235 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),  in xadc_probe()
1241 	xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,  in xadc_probe()
1251 			xadc->threshold[i] = 0xffff;  in xadc_probe()
1253 			xadc->threshold[i] = 0;  in xadc_probe()
1254 		xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1255 			xadc->threshold[i]);  in xadc_probe()
1272 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1273 		iio_trigger_free(xadc->samplerate_trigger);  in xadc_probe()
1275 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1276 		iio_trigger_free(xadc->convst_trigger);  in xadc_probe()
1278 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1281 	clk_disable_unprepare(xadc->clk);  in xadc_probe()
1291 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_remove()  local
1295 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_remove()
1296 		iio_trigger_free(xadc->samplerate_trigger);  in xadc_remove()
1297 		iio_trigger_free(xadc->convst_trigger);  in xadc_remove()
1301 	clk_disable_unprepare(xadc->clk);  in xadc_remove()
1302 	cancel_delayed_work(&xadc->zynq_unmask_work);  in xadc_remove()
1303 	kfree(xadc->data);  in xadc_remove()