94 	unsigned long base = (unsigned long)hwif->hwif_data;  in siimage_selreg()  local
96 	base += 0xA0 + r;  in siimage_selreg()
98 		base += hwif->channel << 6;  in siimage_selreg()
100 		base += hwif->channel << 4;  in siimage_selreg()
101 	return base;  in siimage_selreg()
117 	unsigned long base	= (unsigned long)hwif->hwif_data;  in siimage_seldev()  local
120 	base += 0xA0 + r;  in siimage_seldev()
122 		base += hwif->channel << 6;  in siimage_seldev()
124 		base += hwif->channel << 4;  in siimage_seldev()
125 	base |= unit << unit;  in siimage_seldev()
126 	return base;  in siimage_seldev()
199 	unsigned long base	= (unsigned long)hwif->hwif_data;  in sil_pata_udma_filter()  local
202 	base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;  in sil_pata_udma_filter()
204 	scsc = sil_ioread8(dev, base);  in sil_pata_udma_filter()
250 	unsigned long base	= (unsigned long)hwif->hwif_data;  in sil_set_pio_mode()  local
278 	mode = sil_ioread8(dev, base + addr_mask);  in sil_set_pio_mode()
287 	sil_iowrite8(dev, mode, base + addr_mask);  in sil_set_pio_mode()
305 	unsigned long base	= (unsigned long)hwif->hwif_data;  in sil_set_dma_mode()  local
315 	scsc  = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));  in sil_set_dma_mode()
316 	mode  = sil_ioread8 (dev, base + addr_mask);  in sil_set_dma_mode()
336 	sil_iowrite8 (dev, mode, base + addr_mask);  in sil_set_dma_mode()
366 		unsigned long base	= (unsigned long)hwif->hwif_data;  in siimage_mmio_dma_test_irq()  local
367 		u32 ext_stat		= readl((void __iomem *)(base + 0x10));  in siimage_mmio_dma_test_irq()
457 	unsigned long base, scsc_addr;  in init_chipset_siimage()  local
465 	base = (unsigned long)ioaddr;  in init_chipset_siimage()
482 	sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);  in init_chipset_siimage()
483 	sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);  in init_chipset_siimage()
485 	scsc_addr = base ? (base + 0x4A) : 0x8A;  in init_chipset_siimage()
506 	sil_iowrite8 (dev,       0x72, base + 0xA1);  in init_chipset_siimage()
507 	sil_iowrite16(dev,     0x328A, base + 0xA2);  in init_chipset_siimage()
508 	sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);  in init_chipset_siimage()
509 	sil_iowrite32(dev, 0x43924392, base + 0xA8);  in init_chipset_siimage()
510 	sil_iowrite32(dev, 0x40094009, base + 0xAC);  in init_chipset_siimage()
511 	sil_iowrite8 (dev,       0x72, base ? (base + 0xE1) : 0xB1);  in init_chipset_siimage()
512 	sil_iowrite16(dev,     0x328A, base ? (base + 0xE2) : 0xB2);  in init_chipset_siimage()
513 	sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);  in init_chipset_siimage()
514 	sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);  in init_chipset_siimage()
515 	sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);  in init_chipset_siimage()
517 	if (base && pdev_is_sata(dev)) {  in init_chipset_siimage()
556 	unsigned long base;  in init_mmio_iops_siimage()  local
571 	base = (unsigned long)addr;  in init_mmio_iops_siimage()
573 		base += 0xC0;  in init_mmio_iops_siimage()
575 		base += 0x80;  in init_mmio_iops_siimage()
581 	io_ports->data_addr	= base;  in init_mmio_iops_siimage()
582 	io_ports->error_addr	= base + 1;  in init_mmio_iops_siimage()
583 	io_ports->nsect_addr	= base + 2;  in init_mmio_iops_siimage()
584 	io_ports->lbal_addr	= base + 3;  in init_mmio_iops_siimage()
585 	io_ports->lbam_addr	= base + 4;  in init_mmio_iops_siimage()
586 	io_ports->lbah_addr	= base + 5;  in init_mmio_iops_siimage()
587 	io_ports->device_addr	= base + 6;  in init_mmio_iops_siimage()
588 	io_ports->status_addr	= base + 7;  in init_mmio_iops_siimage()
589 	io_ports->ctl_addr	= base + 10;  in init_mmio_iops_siimage()
592 		base = (unsigned long)addr;  in init_mmio_iops_siimage()
594 			base += 0x80;  in init_mmio_iops_siimage()
595 		hwif->sata_scr[SATA_STATUS_OFFSET]	= base + 0x104;  in init_mmio_iops_siimage()
596 		hwif->sata_scr[SATA_ERROR_OFFSET]	= base + 0x108;  in init_mmio_iops_siimage()
597 		hwif->sata_scr[SATA_CONTROL_OFFSET]	= base + 0x100;  in init_mmio_iops_siimage()