189 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)  in dvc_writel()  argument
191 	writel(val, i2c_dev->base + reg);  in dvc_writel()
194 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)  in dvc_readl()  argument
196 	return readl(i2c_dev->base + reg);  in dvc_readl()
203 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,  in tegra_i2c_reg_addr()  argument
206 	if (i2c_dev->is_dvc)  in tegra_i2c_reg_addr()
211 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,  in i2c_writel()  argument
214 	writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));  in i2c_writel()
218 		readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));  in i2c_writel()
221 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)  in i2c_readl()  argument
223 	return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));  in i2c_readl()
226 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,  in i2c_writesl()  argument
229 	writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);  in i2c_writesl()
232 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,  in i2c_readsl()  argument
235 	readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);  in i2c_readsl()
238 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)  in tegra_i2c_mask_irq()  argument
240 	u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);  in tegra_i2c_mask_irq()
242 	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);  in tegra_i2c_mask_irq()
245 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)  in tegra_i2c_unmask_irq()  argument
247 	u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);  in tegra_i2c_unmask_irq()
249 	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);  in tegra_i2c_unmask_irq()
252 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)  in tegra_i2c_flush_fifos()  argument
255 	u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);  in tegra_i2c_flush_fifos()
257 	i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);  in tegra_i2c_flush_fifos()
259 	while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &  in tegra_i2c_flush_fifos()
262 			dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");  in tegra_i2c_flush_fifos()
270 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)  in tegra_i2c_empty_rx_fifo()  argument
274 	u8 *buf = i2c_dev->msg_buf;  in tegra_i2c_empty_rx_fifo()
275 	size_t buf_remaining = i2c_dev->msg_buf_remaining;  in tegra_i2c_empty_rx_fifo()
278 	val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);  in tegra_i2c_empty_rx_fifo()
287 	i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);  in tegra_i2c_empty_rx_fifo()
299 		val = i2c_readl(i2c_dev, I2C_RX_FIFO);  in tegra_i2c_empty_rx_fifo()
307 	i2c_dev->msg_buf_remaining = buf_remaining;  in tegra_i2c_empty_rx_fifo()
308 	i2c_dev->msg_buf = buf;  in tegra_i2c_empty_rx_fifo()
312 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)  in tegra_i2c_fill_tx_fifo()  argument
316 	u8 *buf = i2c_dev->msg_buf;  in tegra_i2c_fill_tx_fifo()
317 	size_t buf_remaining = i2c_dev->msg_buf_remaining;  in tegra_i2c_fill_tx_fifo()
320 	val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);  in tegra_i2c_fill_tx_fifo()
341 		i2c_dev->msg_buf_remaining = buf_remaining;  in tegra_i2c_fill_tx_fifo()
342 		i2c_dev->msg_buf = buf +  in tegra_i2c_fill_tx_fifo()
346 		i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);  in tegra_i2c_fill_tx_fifo()
362 		i2c_dev->msg_buf_remaining = 0;  in tegra_i2c_fill_tx_fifo()
363 		i2c_dev->msg_buf = NULL;  in tegra_i2c_fill_tx_fifo()
366 		i2c_writel(i2c_dev, val, I2C_TX_FIFO);  in tegra_i2c_fill_tx_fifo()
379 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)  in tegra_dvc_init()  argument
382 	val = dvc_readl(i2c_dev, DVC_CTRL_REG3);  in tegra_dvc_init()
385 	dvc_writel(i2c_dev, val, DVC_CTRL_REG3);  in tegra_dvc_init()
387 	val = dvc_readl(i2c_dev, DVC_CTRL_REG1);  in tegra_dvc_init()
389 	dvc_writel(i2c_dev, val, DVC_CTRL_REG1);  in tegra_dvc_init()
392 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)  in tegra_i2c_clock_enable()  argument
395 	if (!i2c_dev->hw->has_single_clk_source) {  in tegra_i2c_clock_enable()
396 		ret = clk_enable(i2c_dev->fast_clk);  in tegra_i2c_clock_enable()
398 			dev_err(i2c_dev->dev,  in tegra_i2c_clock_enable()
403 	ret = clk_enable(i2c_dev->div_clk);  in tegra_i2c_clock_enable()
405 		dev_err(i2c_dev->dev,  in tegra_i2c_clock_enable()
407 		clk_disable(i2c_dev->fast_clk);  in tegra_i2c_clock_enable()
412 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)  in tegra_i2c_clock_disable()  argument
414 	clk_disable(i2c_dev->div_clk);  in tegra_i2c_clock_disable()
415 	if (!i2c_dev->hw->has_single_clk_source)  in tegra_i2c_clock_disable()
416 		clk_disable(i2c_dev->fast_clk);  in tegra_i2c_clock_disable()
419 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)  in tegra_i2c_init()  argument
426 	err = tegra_i2c_clock_enable(i2c_dev);  in tegra_i2c_init()
428 		dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);  in tegra_i2c_init()
432 	reset_control_assert(i2c_dev->rst);  in tegra_i2c_init()
434 	reset_control_deassert(i2c_dev->rst);  in tegra_i2c_init()
436 	if (i2c_dev->is_dvc)  in tegra_i2c_init()
437 		tegra_dvc_init(i2c_dev);  in tegra_i2c_init()
441 	i2c_writel(i2c_dev, val, I2C_CNFG);  in tegra_i2c_init()
442 	i2c_writel(i2c_dev, 0, I2C_INT_MASK);  in tegra_i2c_init()
445 	clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;  in tegra_i2c_init()
446 	clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<  in tegra_i2c_init()
448 	i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);  in tegra_i2c_init()
450 	if (!i2c_dev->is_dvc) {  in tegra_i2c_init()
451 		u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);  in tegra_i2c_init()
453 		i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);  in tegra_i2c_init()
454 		i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);  in tegra_i2c_init()
455 		i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);  in tegra_i2c_init()
461 	i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);  in tegra_i2c_init()
463 	if (tegra_i2c_flush_fifos(i2c_dev))  in tegra_i2c_init()
466 	if (i2c_dev->hw->has_config_load_reg) {  in tegra_i2c_init()
467 		i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);  in tegra_i2c_init()
468 		while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {  in tegra_i2c_init()
470 				dev_warn(i2c_dev->dev,  in tegra_i2c_init()
478 	tegra_i2c_clock_disable(i2c_dev);  in tegra_i2c_init()
480 	if (i2c_dev->irq_disabled) {  in tegra_i2c_init()
481 		i2c_dev->irq_disabled = 0;  in tegra_i2c_init()
482 		enable_irq(i2c_dev->irq);  in tegra_i2c_init()
492 	struct tegra_i2c_dev *i2c_dev = dev_id;  in tegra_i2c_isr()  local
494 	status = i2c_readl(i2c_dev, I2C_INT_STATUS);  in tegra_i2c_isr()
497 		dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",  in tegra_i2c_isr()
498 			 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),  in tegra_i2c_isr()
499 			 i2c_readl(i2c_dev, I2C_STATUS),  in tegra_i2c_isr()
500 			 i2c_readl(i2c_dev, I2C_CNFG));  in tegra_i2c_isr()
501 		i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;  in tegra_i2c_isr()
503 		if (!i2c_dev->irq_disabled) {  in tegra_i2c_isr()
504 			disable_irq_nosync(i2c_dev->irq);  in tegra_i2c_isr()
505 			i2c_dev->irq_disabled = 1;  in tegra_i2c_isr()
512 			i2c_dev->msg_err |= I2C_ERR_NO_ACK;  in tegra_i2c_isr()
514 			i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;  in tegra_i2c_isr()
518 	if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {  in tegra_i2c_isr()
519 		if (i2c_dev->msg_buf_remaining)  in tegra_i2c_isr()
520 			tegra_i2c_empty_rx_fifo(i2c_dev);  in tegra_i2c_isr()
525 	if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {  in tegra_i2c_isr()
526 		if (i2c_dev->msg_buf_remaining)  in tegra_i2c_isr()
527 			tegra_i2c_fill_tx_fifo(i2c_dev);  in tegra_i2c_isr()
529 			tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);  in tegra_i2c_isr()
532 	i2c_writel(i2c_dev, status, I2C_INT_STATUS);  in tegra_i2c_isr()
533 	if (i2c_dev->is_dvc)  in tegra_i2c_isr()
534 		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);  in tegra_i2c_isr()
537 		BUG_ON(i2c_dev->msg_buf_remaining);  in tegra_i2c_isr()
538 		complete(&i2c_dev->msg_complete);  in tegra_i2c_isr()
543 	tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |  in tegra_i2c_isr()
546 	i2c_writel(i2c_dev, status, I2C_INT_STATUS);  in tegra_i2c_isr()
547 	if (i2c_dev->is_dvc)  in tegra_i2c_isr()
548 		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);  in tegra_i2c_isr()
550 	complete(&i2c_dev->msg_complete);  in tegra_i2c_isr()
554 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,  in tegra_i2c_xfer_msg()  argument
561 	tegra_i2c_flush_fifos(i2c_dev);  in tegra_i2c_xfer_msg()
566 	i2c_dev->msg_buf = msg->buf;  in tegra_i2c_xfer_msg()
567 	i2c_dev->msg_buf_remaining = msg->len;  in tegra_i2c_xfer_msg()
568 	i2c_dev->msg_err = I2C_ERR_NONE;  in tegra_i2c_xfer_msg()
569 	i2c_dev->msg_read = (msg->flags & I2C_M_RD);  in tegra_i2c_xfer_msg()
570 	reinit_completion(&i2c_dev->msg_complete);  in tegra_i2c_xfer_msg()
574 			(i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |  in tegra_i2c_xfer_msg()
576 	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);  in tegra_i2c_xfer_msg()
579 	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);  in tegra_i2c_xfer_msg()
596 	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);  in tegra_i2c_xfer_msg()
599 		tegra_i2c_fill_tx_fifo(i2c_dev);  in tegra_i2c_xfer_msg()
602 	if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)  in tegra_i2c_xfer_msg()
606 	else if (i2c_dev->msg_buf_remaining)  in tegra_i2c_xfer_msg()
608 	tegra_i2c_unmask_irq(i2c_dev, int_mask);  in tegra_i2c_xfer_msg()
609 	dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",  in tegra_i2c_xfer_msg()
610 		i2c_readl(i2c_dev, I2C_INT_MASK));  in tegra_i2c_xfer_msg()
612 	time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,  in tegra_i2c_xfer_msg()
614 	tegra_i2c_mask_irq(i2c_dev, int_mask);  in tegra_i2c_xfer_msg()
617 		dev_err(i2c_dev->dev, "i2c transfer timed out\n");  in tegra_i2c_xfer_msg()
619 		tegra_i2c_init(i2c_dev);  in tegra_i2c_xfer_msg()
623 	dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",  in tegra_i2c_xfer_msg()
624 		time_left, completion_done(&i2c_dev->msg_complete),  in tegra_i2c_xfer_msg()
625 		i2c_dev->msg_err);  in tegra_i2c_xfer_msg()
627 	if (likely(i2c_dev->msg_err == I2C_ERR_NONE))  in tegra_i2c_xfer_msg()
635 	if (i2c_dev->msg_err == I2C_ERR_NO_ACK)  in tegra_i2c_xfer_msg()
636 		udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));  in tegra_i2c_xfer_msg()
638 	tegra_i2c_init(i2c_dev);  in tegra_i2c_xfer_msg()
639 	if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {  in tegra_i2c_xfer_msg()
651 	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);  in tegra_i2c_xfer()  local
655 	if (i2c_dev->is_suspended)  in tegra_i2c_xfer()
658 	ret = tegra_i2c_clock_enable(i2c_dev);  in tegra_i2c_xfer()
660 		dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);  in tegra_i2c_xfer()
672 		ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);  in tegra_i2c_xfer()
676 	tegra_i2c_clock_disable(i2c_dev);  in tegra_i2c_xfer()
682 	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);  in tegra_i2c_func()  local
686 	if (i2c_dev->hw->has_continue_xfer_support)  in tegra_i2c_func()
755 	struct tegra_i2c_dev *i2c_dev;  in tegra_i2c_probe()  local
782 	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);  in tegra_i2c_probe()
783 	if (!i2c_dev)  in tegra_i2c_probe()
786 	i2c_dev->base = base;  in tegra_i2c_probe()
787 	i2c_dev->div_clk = div_clk;  in tegra_i2c_probe()
788 	i2c_dev->adapter.algo = &tegra_i2c_algo;  in tegra_i2c_probe()
789 	i2c_dev->adapter.quirks = &tegra_i2c_quirks;  in tegra_i2c_probe()
790 	i2c_dev->irq = irq;  in tegra_i2c_probe()
791 	i2c_dev->cont_id = pdev->id;  in tegra_i2c_probe()
792 	i2c_dev->dev = &pdev->dev;  in tegra_i2c_probe()
794 	i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");  in tegra_i2c_probe()
795 	if (IS_ERR(i2c_dev->rst)) {  in tegra_i2c_probe()
797 		return PTR_ERR(i2c_dev->rst);  in tegra_i2c_probe()
800 	ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",  in tegra_i2c_probe()
801 					&i2c_dev->bus_clk_rate);  in tegra_i2c_probe()
803 		i2c_dev->bus_clk_rate = 100000; /* default clock rate */  in tegra_i2c_probe()
805 	i2c_dev->hw = &tegra20_i2c_hw;  in tegra_i2c_probe()
810 		i2c_dev->hw = match->data;  in tegra_i2c_probe()
811 		i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,  in tegra_i2c_probe()
814 		i2c_dev->is_dvc = 1;  in tegra_i2c_probe()
816 	init_completion(&i2c_dev->msg_complete);  in tegra_i2c_probe()
818 	if (!i2c_dev->hw->has_single_clk_source) {  in tegra_i2c_probe()
824 		i2c_dev->fast_clk = fast_clk;  in tegra_i2c_probe()
827 	platform_set_drvdata(pdev, i2c_dev);  in tegra_i2c_probe()
829 	if (!i2c_dev->hw->has_single_clk_source) {  in tegra_i2c_probe()
830 		ret = clk_prepare(i2c_dev->fast_clk);  in tegra_i2c_probe()
832 			dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);  in tegra_i2c_probe()
837 	i2c_dev->clk_divisor_non_hs_mode =  in tegra_i2c_probe()
838 			i2c_dev->hw->clk_divisor_std_fast_mode;  in tegra_i2c_probe()
839 	if (i2c_dev->hw->clk_divisor_fast_plus_mode &&  in tegra_i2c_probe()
840 		(i2c_dev->bus_clk_rate == 1000000))  in tegra_i2c_probe()
841 		i2c_dev->clk_divisor_non_hs_mode =  in tegra_i2c_probe()
842 			i2c_dev->hw->clk_divisor_fast_plus_mode;  in tegra_i2c_probe()
844 	clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);  in tegra_i2c_probe()
845 	ret = clk_set_rate(i2c_dev->div_clk,  in tegra_i2c_probe()
846 			   i2c_dev->bus_clk_rate * clk_multiplier);  in tegra_i2c_probe()
848 		dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);  in tegra_i2c_probe()
852 	ret = clk_prepare(i2c_dev->div_clk);  in tegra_i2c_probe()
854 		dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);  in tegra_i2c_probe()
858 	ret = tegra_i2c_init(i2c_dev);  in tegra_i2c_probe()
864 	ret = devm_request_irq(&pdev->dev, i2c_dev->irq,  in tegra_i2c_probe()
865 			tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);  in tegra_i2c_probe()
867 		dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);  in tegra_i2c_probe()
871 	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);  in tegra_i2c_probe()
872 	i2c_dev->adapter.owner = THIS_MODULE;  in tegra_i2c_probe()
873 	i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;  in tegra_i2c_probe()
874 	strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",  in tegra_i2c_probe()
875 		sizeof(i2c_dev->adapter.name));  in tegra_i2c_probe()
876 	i2c_dev->adapter.dev.parent = &pdev->dev;  in tegra_i2c_probe()
877 	i2c_dev->adapter.nr = pdev->id;  in tegra_i2c_probe()
878 	i2c_dev->adapter.dev.of_node = pdev->dev.of_node;  in tegra_i2c_probe()
880 	ret = i2c_add_numbered_adapter(&i2c_dev->adapter);  in tegra_i2c_probe()
889 	clk_unprepare(i2c_dev->div_clk);  in tegra_i2c_probe()
892 	if (!i2c_dev->hw->has_single_clk_source)  in tegra_i2c_probe()
893 		clk_unprepare(i2c_dev->fast_clk);  in tegra_i2c_probe()
900 	struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);  in tegra_i2c_remove()  local
901 	i2c_del_adapter(&i2c_dev->adapter);  in tegra_i2c_remove()
903 	clk_unprepare(i2c_dev->div_clk);  in tegra_i2c_remove()
904 	if (!i2c_dev->hw->has_single_clk_source)  in tegra_i2c_remove()
905 		clk_unprepare(i2c_dev->fast_clk);  in tegra_i2c_remove()
913 	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);  in tegra_i2c_suspend()  local
915 	i2c_lock_adapter(&i2c_dev->adapter);  in tegra_i2c_suspend()
916 	i2c_dev->is_suspended = true;  in tegra_i2c_suspend()
917 	i2c_unlock_adapter(&i2c_dev->adapter);  in tegra_i2c_suspend()
924 	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);  in tegra_i2c_resume()  local
927 	i2c_lock_adapter(&i2c_dev->adapter);  in tegra_i2c_resume()
929 	ret = tegra_i2c_init(i2c_dev);  in tegra_i2c_resume()
932 		i2c_unlock_adapter(&i2c_dev->adapter);  in tegra_i2c_resume()
936 	i2c_dev->is_suspended = false;  in tegra_i2c_resume()
938 	i2c_unlock_adapter(&i2c_dev->adapter);  in tegra_i2c_resume()